H03K 19/09482
Using a combination of enhancement and depletion transistors
Official title: {using a combination of enhancement and depletion transistors}
H03K19/09482 (Using a combination of enhancement and depletion transistors) appears on 30 US grants and 14 published applications in this corpus.
Search patents in H03K- Granted patents
- 30
- Published applications
- 14
- Assignees
- 29
- Inventors
- 56
- Latest grant
- 26 May 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 1 | 0 |
| 1977 | 1 | 0 |
| 1978 | 3 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 1 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 1 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 1 | 0 |
| 2001 | 1 | 0 |
| 2002 | 1 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 1 | 2 |
| 2006 | 1 | 1 |
| 2007 | 1 | 1 |
| 2008 | 0 | 2 |
| 2009 | 1 | 0 |
| 2010 | 0 | 0 |
| 2011 | 0 | 0 |
| 2012 | 0 | 1 |
| 2013 | 1 | 2 |
| 2014 | 1 | 0 |
| 2015 | 0 | 0 |
| 2016 | 1 | 2 |
| 2017 | 1 | 0 |
| 2018 | 0 | 1 |
| 2019 | 1 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 1 |
| 2025 | 0 | 0 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Semiconductor device including delay-enhanced inverter circuit and method of forming same26 May 2026US 12,640,738 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Data holding device, nonvolatile data holding device, and data reading method5 Mar 2019US 10,224,101 B2Rohm Co., Ltd.
- Adaptive dynamic keeper circuit3 Jan 2017US 9,537,485 B2QUALCOMM Incorporated
- Method and apparatus for improving a load independent buffer29 Nov 2016US 9,509,292 B2Intel Corporation
- Semiconductor apparatus16 Sep 2014US 8,836,370 B2SK hynix Inc.
- Semiconductor device including delay-enhanced inverter circuit and method of forming same17 Sep 2026US 2026/0280564 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor device iincluding delay-enhanced inverter circuit and method of forming same8 Aug 2024US 2024/0267049 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Data holding device, nonvolatile data holding device, and data reading method19 Apr 2018US 2018/0108414 A1Rohm Co., Ltd.
- Method and apparatus for improving a load independent buffer18 Aug 2016US 2016/0241244 A1
- Adaptive dynamic keeper circuit7 Apr 2016US 2016/0099713 A1QUALCOMM Incorporated
Most cited
By later US patents
- Mosfet logical circuit with increased noise margin50US 4,532,439 ATokyo Shibaura Denki Kabushiki Kaisha · 1985
- Cascode circuit employing a depletion-mode, GaN-based FET47US 7,501,670 B2Velox Semiconductor Corporation · 2009
- CMOS-inverter40US 4,675,544 ASiemens Aktiengesellschaft · 1987
- Complementary MOS logic circuit28US 4,064,405 AWestinghouse Electric Corp. · 1977
- Programmable logic gates and networks23US 4,495,427 ARCA Corporation · 1985