Mosfet logical circuit with increased noise margin

A oscillator circuit comprising:

• a first circuit consisting of at least one MOSFET of a first conductivity type having a gate connected to an input terminal and having a first current path with one end connected to an output terminal;
• a second circuit consisting of at least one MOSFET of a second conductivity type having a gate connected to said input terminal and having a second current path with one end connected to said output terminal;
• a crystal oscillator interposed between said input and output terminals;
• a depletion-type MOSFET of said second conductivity type interposed between another end of said first current path and a first power source, having a gate connected to said output terminal and having a threshold voltage, the absolute value of which is larger than that of said at least one first conductivity-type MOSFET;
• and
• a depletion-type MOSFET of said first conductivity type, interposed between another end of said second current path and a second power source, having a gate connected to said output terminal and having a threshold voltage, the absolute value of which is larger than that of said at least one second conductivity-type MOSFETS.

A memory circuit, including digit lines and a word line carrying a word line signal, comprising:

• a first complementary type MOSFET inverter connected to be powered across first and second power sources, having input and output terminals and including at least one MOSFET of a first conductivity type which has a gate connected to the first inverter input terminal and a first current path with one end connected to the first inverter output terminal;
• a second complementary type MOSFET inverter, connected to be powered across said first and second power sources, having input and output terminals and comprising at least one MOSFET of a second conductivity type which has a gate connected to the second inverter input terminal and a second current path with one end connected to the second inverter output terminal, wherein the output terminal of said fist inverter is coupled to the input terminal of said second inverter and the output terminal of said second inverter is coupled to the input terminal of said first inverter;
• transfer gate means for coupling said inverter output terminals to said digit lines in accordance with said word line signal;
• a depletion-type MOSFET of said second conductivity type interposed between another end of said first current path and a first power source, having a gate connected to said first inverter output terminal and having a threshold voltage, the absolute value of which is larger than that of said at least one first conductivity-type MOSFET;
• and
• a depletion-type MOSFET of said first conductivity type, interposed between another end of said second current path and a second power source, having a gate connected to said second inverter output terminal and having a threshold voltage, the absolute value of which is larger than that of said at least one second conductivity-type MOSFET.