Programmable logic gates and networks

A method for providing electrically erasable, electrically programmable logic circuitry comprising the steps of:

• making connections for at least one logic output terminal to each of two supply voltage terminals, at least one of said connections being a selectively made connection through the principal current conduction paths of respective transistors, said selectively made connection including the principal current conduction paths of a plurality of switching transistors, each of which paths during a time period of normal operation is switched into conduction or non-conduction responsive to signal applied from a respective logic input terminal to the control electrode of the corresponding switching transistor, and including the channel of at least one programmable-threshold-voltage (or programmable-V.sub.T) field effect transistor;
• and
• applying for a time previous to said time period of normal operation a programming voltage to each said programmable-V.sub.T field effect transistor for conditioning it to be in a selected one of two states continuously during said time period of normal operation thereafter, either the state where it is so strongly conditioned for depletion-mode operation its channel functions as a short-circuit or the state where it is so strongly conditioned for enhancement-mode operation its channel functions as an open-circuit;
• wherein the step of applying programming voltage includes
• applying programming voltage to the gate electrode of each said programmable-V.sub.T field effect transistor through one of said logic input terminals, and
• applying a reference voltage to the substrate and to the drain and source electrodes of each of said programmable-V.sub.T field effect transistors.

A method for providing electrically erasable, electrically programmable logic circuitry comprising the steps of:

• making selective connections of at least one logic output terminal to each of first and second supply voltage terminals at different times during a period of normal operation through the principal current conduction paths of respective transistors, each selective connection including the principal conduction paths of respective switching transistors switched into conduction or non-conduction responsive to signals applied from logic input terminals to their control electrodes outside their principal conduction paths, and each selective connection including the channels of respective programmable-threshold-voltage (or programmable-V.sub.T) field effect transistors;
• and
• applying, for a time previous to said period of normal operation, at least one programming voltage to both of a respective pair of said programmable-V.sub.T field effect transistors, one being in the selective connection of a said logic output terminal to said first supply voltage terminal and the other being in the selective connection of that logic output terminal to said second supply voltage terminal, for so strongly conditioning one of the pair for depletion-mode operation during the period of normal operation thereafter that its channel functions as a short-circuit and so strongly conditioning the other of the pair of enhancement-mode operation during the period of normal operation thereafter that its channel fucntions as an open-circuit.

A method for reducing the number of programming lines in a network comprising field effect transistors interconnected by means including first and second electrically programmable elements, said first electrically programmable element to be programmed for conduction when said second electrically programmable elements is to be programmed for non-conduction, and vice versa, for helping to make selective respective connections of a network output terminal to one of two operating voltage terminals, said method comprising the steps of:

• using for said first electrically programmable element the channel of a first field effect transistor of a first conductivity type, which has a charge-injecting electrode structure, and which has in addition to its control gate electrode a floating gate between which and said charge-injecting electrode structure thereof a static charge may be placed responsive to a programming voltage applied between its control gate electrode and that charge-injecting electrode structure, for altering its threshold voltage;
• using for said second electrically programmable element the channel of a second field effect transistor of a second conductivity type complementary to said first conductivity type, which has a charge-injecting electrode structure analogous to that of said first field effect transistor and which has in addition to its control gate electrode a floating gate between which and said charge-injecting electrode structure thereof a static charge may be placed responsive to a programming voltage applied between its control gate electrode and that charge-injecting electrode structure, for altering its threshold voltage and
• connecting the control gate electrodes of these first and second field effect transistors to the same programming line.

A method for eliminating the need for separate terminals specifically for application of programming signals in a network comprising field effect transistors with ones of their electrodes each connected to one of a plurality of network input terminals consecutively ordinally numbered at least first through n.sup.th and the others of their electrodes interconnected by means including a plurality of electrically programmable elements, a first of these electrically programmable elements to be programmed for conduction when a second of them is to be programmed for non-conduction, and vice versa, for helping to make selective respective connections of a network output terminal to one of two operating voltage terminals, said method comprising the steps of:

• using for said first electrically programmable element the parallelly connected channels of a first plurality of further field effect transistors consecutively ordinally numbered first through n.sup.th, each of which has a control gate electrode connected to the network input terminal similarly ordinally numbered and has a floating gate electrode on which an electrostatic charge may be placed responsive to a programming voltage applied to its control gate electrode;
• and
• using for said second electrically programmable element the serially connected channels of a second plurality of further field effect transistors consecutively ordinally numbered first through n.sup.th, each of which has a control gate electrode connected to the network input terminal similarly ordinally numbered and has a floating gate electrode on which an electrostatic charge may be placed responsive to a programming voltage applied to its control gate electrode.

A method for programmably providing either a conductive or a selectively conductive path between first and second nodes, using between said first and second nodes a programmable element comprising:

• an input terminal for receiving control signal voltages in a normal operating range or programming voltages outside said normal operating range;
• a first field effect transistor having a gate electrode connected to said input terminal, being of a type having a threshold voltage alterable responsive to programming voltages received at its gate electrode, and having a channel with first and second ends respectively connected at said first node and at said second node;
• and
• a second field effect transistor having a gate electrode connected to said input terminal, being of a type having a threshold voltage characteristic unaffected after application of programming voltages via said input terminal to the gate of said first field effect transistor, and having a channel with first and second ends respectively connected at said first node and at said second node, which method further includes the alternative steps of:
• applying a programming voltage of a first sense to said input terminal, which programming voltage is of an amplitude large enough to condition said first transistor to be so strongly depletion-mode in its conduction characteristic that its channel is conductive for all control signals in said normal operating range applied to its gate electrode, whereby said conductive path is continuously provided between said first and second nodes by the channel of said first transistor bypassing the channel of said second transistor until the conduction characteristic of said first transistor is changed by re-programming;
• and
• applying a programming voltage of a second sense opposite to the first sense to said input terminal, which programming voltage is of an amplitude large enough to condition said first transistor to be so strongly enhancement-mode in its conduction characteristic that its channel is non-conductive for all control signals in said normal operating range applied to its gate electrode, whereby the selectively conductive path between said first and second nodes is provided solely through the channel of said second transistor, until the conduction characteristic of said first transistor is changed by re-programming.

A method for programmably providing either a selectively conductive path or no path for conduction between first and second nodes, using between said first and second nodes a programmable element comprising:

• an input terminal for receiving control signal voltages in a normal operating range or programming voltages outside said normal operating range;
• a first field effect transistor having a gate electrode connected to said input terminal, being of a type having a threshold voltage alterable responsive to programming voltages received at its gate electrode, and having a channel with first and second ends, its first end being connected to said first node;
• a second field effect transistor having a gate electrode connected to said input terminal, being of a type having a threshold voltage characteristic unaffected after application of programming voltages via said input terminal to the gate of said first field effect transistor, and having a channel with first and second ends, its first end being connected to the second end of the channel of said first field effect transistor, and its second end being connected to said second node, which method invariably leaves said first field effect transistor with its channel conditioned to function either as an effective open-circuit or as an effective short circuit for the channel current of said second transistor as tends to flow in response to control signal voltages in said normal operating range, to cause the conduction characteristics of said selectively conductive path to be essentially attributable to the conduction characteristics of said second transistor rather than to those of said first transistor, and which method accordingly comprises the alternative steps of:
• applying a programming voltage of a first sense to said input terminal, which programming voltage is of an amplitude large enough to condition said first transistor to be so strongly depletion-mode in its conduction characteristics that its channel is conductive for all control signals in said normal operating range applied to its gate electrode, whereby said selectively conductive path is provided between said first and second nodes through the channels of said first and second transistors until the conduction characteristic of said first transistor is changed by re-programming;
• and
• applying a programming voltage of a second sense opposite to the first sense to said input terminal, which programming voltage is of an amplitude large enough to condition said first transistor to be so strongly enhancement-mode in its conduction characteristics that its channel is non-conductive for all control signals in said normal operating range applied to its gate electrode, whereby said first transistor interrupts conduction between said first and second nodes until its conduction characteristic is changed by re-programming.

A programmable gate for providing a selected type of controlled conduction between first and second nodes, said programmable gate comprising:

• a plurality, n in number, of input terminals, for receiving conduction controlling signals within a prescribed range during a period of normal operation, and for receiving selection signals outside said prescribed range during a programming interval previous to said period of normal operation, which selection signals select the type of controlled conduction provided in the following said period of normal operation;
• a first plurality, n in number, of field effect transistors having respective gate electrodes connected to respective ones of said input terminals, having threshold voltages unaffected by signals within said prescribed range but electrically alterable responsive to programming voltages applied to their gates via said input terminals, and having respective channels in a series connection between said first and second nodes for selecting the type of controlled conduction between said first and second nodes, dependent on whether selection signals last applied to the gate electrodes of the field effect transistors in said first plurality have rendered each sufficiently depletion-mode in conduction characteristic that its channel is conductive under all conduction controlling signal conditions as obtain during said period of normal operation or sufficiently enhancement-mode in conduction characteristic that its channel is non-conductive under all conduction controlling signal conditions as obtain during said period of normal operation;
• and
• a second plurality, n in number, of field effect transistors having respective gate electrodes connected to respective ones of said input terminals, having threshold voltage characteristics unaffected by signals within said prescribed range and programming voltages outside said prescribed range applied via said input terminals, and having respective channels in parallel connections with respective ones of the channels of said first plurality of field effect transistors, the channels of field effect transistors in said second plurality parallelled by non-conductive channels of field effect transistors in said first plurality providing control of the conduction between said first and second nodes responsive to the conduction controlling signals received at the input terminals connected to the gate electrodes of those field effect transistors in said second plurality.

A programmable gate for selectively providing conduction between first and second nodes as a programmably selected one of a set of OR responses to logic signals, said programmable gate comprising:

• a plurality, n in number, of input terminals;
• a first plurality, n in number, of field effect transistors having respective gate electrodes connected to respective ones of said input terminals, having respective channels the first ends of which connect to said first node, and having threshold voltages electrically alterable responsive to programming voltages applied to their gates via said input terminals, for conditioning each of their channels either to be conductive for all logic signal levels or to be non-conductive for all logic signal levels until possible reprogramming;
• a second plurality, n in number, of field effect transistors having respective gate electrodes connected to respective ones of said input terminals, having threshold voltage characteristics unaffected after application of programming voltage via said input terminals, and having respective channels connected at their first ends to respective ones of the second ends of the channels of said first plurality of field effect transistors and connected at their second ends to said second node;
• and
• means for applying logic signals to said input terminals connecting to those of said second plurality of field effect transistors having their channels in series connection with the channels of those of said first plurality of field effect transistors conditioned to be conductive for all logic signals, the application of said logic signals being made following application of programming voltages, said logic signals being apt to be at times such as to simultaneously condition more than one of said second plurality of field effect transistors to complete a respective conduction path between first and second nodes.

A programmable gate with selectively conductive current conduction path between first and second nodes, said programmable gate comprising:

• a plurality, n in number, of input terminals for logic voltages in a normal range of logic levels and for programming voltages outside said normal range;
• a first plurality, n in number, of field effect transistors of a first conductivity type, having respective gates connected to respective ones of said input terminals, having threshold voltage characteristics unaffected by logic or by programming voltages received at their gates, and having respective channels;
• a second plurality, n in number, of field effect transistors of said first conductivity type, having respective gates connected to respective ones of said input terminals, having threshold voltages electrically alterable responsive to programming voltages but not to logic voltages received at their gates from respective ones of said input terminals, and having respective channels connected in respective parallel combinations with respective ones of the channels of field effect transistors in said first plurality;
• and
• programmable switch means having a selectively conductive path therethrough for selectively completing a serial connection of said parallel combinations between said first and second nodes, said path being programmed for non-conduction only in response to programming voltages at said input terminals being such as to alter the threshold voltages all of said second plurality of transistors to thereafter condition their channels for simultaneous conduction irrespective of logic voltages.

A programmable gate with selectively conductive current conduction path between first and second nodes, said programmable gate comprising:

• a plurality, n in number, of input terminals for logic voltages in a normal range of logic levels and for programming voltages outside said normal range;
• a first plurality, n in number, of field effect transistors of a first conductivity type having respective gates connected to respective ones of said input terminals, having threshold voltage characteristics unaffected by logic or programming voltages received at their gates, and having respective channels connected at their first ends to said first node the conductivity of which channels is controlled by the logic voltages received at their gates;
• a second plurality, n in number, of field effect transistors of said first conductivity type, having respective gates connected to respective ones of said input terminals, having threshold voltages electrically alterable responsive to programming voltages but not to logic voltages received at their gates, and having respective channels connected at their first ends to respective ones of the second ends of the channels of field effect transistors in said first plurality and connected at their second ends to said second node;
• and
• programmable switch means having a selectively conductive path therethrough for selectively connecting said first and second nodes, said path being programmed for conduction only in response to programming voltages at said input terminals being such as to alter the threshold voltages of all of said second plurality of transistors to thereafter condition their channels for simultaneous non-conduction irrespective of logic voltages.

A COS/MOS logic array having first and second supply voltage terminals;

• a multiplicity m of logic input terminals consecutively ordinally numbered first through m.sup.th ;
• at least one logic output terminal;
• a multiplicity m of n-channel logic FET's associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having channels arranged with intervening nodal connections in a first network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said first supply voltage terminal, and having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own;
• and a multiplicity m of p-channel logic FET's associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having channels arranged with intervening nodal connections in a second network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said second supply voltage terminal, said first and second networks being duals of each other insofar as impedance and admittance are concerned, and having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own-- said COS/MOS logic array modified by inclusion of programmable switch elements each electrically programmable either to be essentially conductive or to be essentially non-conductive over the range of normal logic levels;
• said programmable switch elements being connected so that:
• a respective programmable switch element parallels the channel of each logic FET that is serially connected with another logic FET, the channel of each logic FET that is serially connected with a parallel combination of circuit branches, and each parallel combination of circuit branches that is serially connected with a logic FET;
• and
• a respective programmable switch element is interposed in series with the channel of each logic FET that is parallelly connected with another logic FET, the channel of each logic FET that is parallelly connected with a series combination of circuit branches, and each series combination of circuit branches that is parallelly connected with a logic FET.

A programmable logic gate comprising:

• first and second field effect transistors of a first conductivity type and third and fourth field effect transistors of a second conductivity type complementary to the first, said transistors having respective channels the ends of which are defined by respective source and drain electrodes and having respective gate electrodes;
• fifth, sixth, seventh and eighth field effect transistors with programmable threshold voltages, having respective channels the ends of which are defined by respective source and drain electrodes and having respective gate electrodes for receiving programming voltages;
• first and second supply voltage terminals;
• a first input terminal connected to the gate electrodes of said first and third transistors;
• a second input terminal connected to the gate electrodes of said second and fourth transistors;
• an output terminal, between which and said first supply voltage terminal there is a series connection including the channels of said first and fifth transistors and a series connection including the channels of said second and sixth transistors, and between which and said second supply voltage terminal there is a series connection including the parallelled channels of said third and seventh transistors and including the parallelled channels of said fourth and eighth transistors;
• means for applying respective programming voltages between the gate electrodes of said fifth and seventh transistors and appropriate others of their electrodes to condition the channel of one to be conductive and the channel of the other non-conductive;
• and
• means for applying respective programming voltages between the gate electrodes of said sixth and eighth transistors and appropriate others of their electrodes to condition the channel of one to be conductive and the channel of the other to be non-conductive.

A programmable logic gate comprising:

• first, second, third, and fourth field effect transistors of a first conductivity type and
• fifth, sixth, seventh and eighth field effect transistors of a second conductivity type complementary to said first conductivity type, each of said transistors having a respective source, respective drain and respective gate, and requiring a threshold potential between its source and gate be exceeded before it exhibits substantial conduction between its source and drain, the threshold potentials of said even-numbered transistors being substantially fixed in level and the threshold potential of each of said odd-numbered transistors being electrically alterable by application of potential between its gate and at least one of its source and drain;
• a first supply voltage terminal to which the sources of said first and third transistors connect;
• a second supply voltage terminal to which the sources of said fifth and sixth transistors connect;
• a first input terminal connecting to the gates of said second and sixth transistors;
• a second input terminal connecting to the gates of said fourth and eighth transistors;
• an output terminal to which the drains of said second and fourth transistors connect;
• a first node between the drain of said first transistor and the source of said second transistor;
• a second node between the drain of said third transistor and the source of said fourth transistor;
• a third node to which the drains of said fifth and sixth transistors and the sources of said seventh and eighth transistors connect;
• a fourth node to which the drains of said seventh and eighth transistors connect;
• means for connecting said fourth node to said output terminal at least at selected times during operation as a logic gate;
• and
• means for selectively applying at other times respective programming potentials between the gate of each of said odd-numbered transistors and at least one of its source and drain for programming its threshold potential, including
• means for applying a reference potential at said other times to said at least one of its source and drain of each of said odd-numbered transistors.

A programmable logic gate comprising:

• first, second, third, and fourth field effect transistors of a first conductivity type and
• fifth, sixth, seventh and eighth field effect transistors of a second conductivity type complementary to said first conductivity type, each of said transistors having a respective source, respective drain and respective gate, having a substrate that it may share with other field effect transistors of the same conductivity type, and requiring a threshold potential between its source and gate be exceeded before it exhibits substantial conduction between its source and drain, the threshold potentials of said even-numbered transistors being substantially fixed in level and the threshold potential of each of said odd-numbered transistors being electrically alterable by application of potential between its gate and its substrate;
• a first supply voltage terminal to which the sources of said first and third transistors connect;
• a second supply voltage terminal to which the sources of said fifth and sixth transistors connect;
• a first input terminal connecting to the gates of said second and sixth transistors;
• a second input terminal connecting to the gates of said fourth and eighth transistors;
• an output terminal to which the drains of said second and fourth transistors connect;
• a first node between the drain of said first transistor and the source of said second transistor;
• a second node between the drain of said third transistor and the source of said fourth transistor;
• a third node to which the drains of said fifth and sixth transistors and the sources of said seventh and eighth transistors connect;
• a fourth node to which the drains of said seventh and eighth transistors connect;
• means for connecting said fourth node to said output terminal at least at selected times during operation as a logic gate;
• and
• means for selectively applying at other times respective programming potentials between the gate of each of said odd-numbered transistors and its substrate for programming its threshold potential, including
• means for applying a reference potential at said other times to the substrates of each of said odd-numbered transistors.

A programmable logic gate comprising:

• a first plurality, n in number, of floating-gate MOSFET's, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control gate electrode;
• a second plurality, n in number, of floating-gate MOSFET's, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control gate electrode;
• a plurality, n in number, of further transistors of a first conductivity type, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control electrode;
• a plurality, n in number, of further transistors of a second conductivity type, complementary to said first conductivity type, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control electrode;
• a plurality, n in number, of input terminals, consecutively ordinally numbered first through n.sup.th, each of which input terminals connects to the control electrodes of the pair of said further transistors having ordinal numbers the same as its ordinal number;
• first and second supply voltage terminals;
• an output terminal;
• series connections between said first supply voltage terminal and said output terminal of each of the principal current conduction paths of said floating-gate MOSFET's of said first plurality with the principal current conduction path of the one of said further transistors of said first conductivity type bearing the same ordinal number;
• parallel connections of each of the principal current conduction paths of said floating-gate MOSFET's of said second plurality with the principal current conduction path of the one of said further transistors of said second conductivity type having the same ordinal number, which parallel connections are serially connected between said output terminal and said supply voltage terminal;
• and
• means selectively applying a respective programming potential between the gate electrode of each of said floating-gate MOSFET's and one of the ends of its principal current conduction path for programming that path to be relatively low resistance or relatively high resistance.

A programmable logic array comprising:

• first and second supply voltage terminals;
• a plurality, m in number, of logic input terminals consecutively ordinally numbered first through m.sup.th ;
• a logic output terminal;
• a first plurality, m in number, of transistors with fixed threshold voltages, consecutively ordinally numbered first through m.sup.th, having respective gates connected to respective logic input terminals having the same ordinal numbers as their own, and having respective channels;
• a second plurality, m in number, of transistors with fixed threshold voltages, consecutively ordinally numbered m-plus-first through 2m.sup.th, having respective gates connected to respective logic input terminals having ordinal numbers smaller by m than their own, and having respective channels, each pair of said transistors with fixed thresholds having ordinal numbers differing by m being of complementary conductivity types to each other;
• an even-numbered plurality, 2p in number, of transistors with programmable threshold voltages, consecutively ordinally numbered first through 2p.sup.th, having respective gates and having respective channels, the threshold voltage of each of which transistors is electrically alterable by application of a respective programming voltage to its gate;
• means for applying, at selected times, programming voltages to the gates of said transistors with programmable threshold voltages;
• a first network connection with intervening nodes of the channels of said first plurality of transistors with fixed threshold voltages and each of said plurality of transistors with programmable threshold voltages and with ordinal number no larger than p, for selectively connecting said output logic terminal to said first supply voltage terminal;
• a second network connection with intervening nodes of the channels of said second plurality of transistors with fixed threshold voltages and each of said plurality of transistors with programmable threshold voltages and with ordinal numbers larger then p, for selectively connecting said output logic terminal to said second supply voltage terminal, said first and second network connections being duals of each other insofar as impedance and admittance characteristics of their selective connections are concerned;
• and
• means for applying at said selected times, voltages to those of said intervening nodes in said first and second network connection as necessary to program those transistors with programmable threshold voltages.

A programmable logic array comprising:

• first and second supply voltage terminals;
• a plurality, m in number, of logic input terminals consecutively ordinally numbered first through m.sup.th ;
• a number p, at least one, of programming lines, consecutively ordinally numbered first through p.sup.th ;
• a logic output terminal;
• a first plurality, m in number, of transistors with fixed threshold voltages, consecutively ordinally numbered first through m.sup.th, having respective gates connected to respective logic input terminals having the same ordinal numbers as their own, and having respective channels;
• a second plurality, m in number, of transistors with fixed threshold voltages, consecutively ordinally numbered m-plus-first through 2m.sup.th, having respective gates connected to respective logic input terminals having ordinal numbers smaller by m than their own, and having respective channels, each pair of said transistors with fixed thresholds having ordinal numbers differing by m being of complementary conductivity types to each other;
• a plurality, 2p in number, of transistors with programmable threshold voltages, consecutively ordinally numbered first through 2p.sup.th, having respective gates and having respective channels, the threshold voltage of each of which transistors is electrically alterable by application of a respective programming voltage to its gate, each pair of said transistors with programmable threshold voltages having ordinal numbers differing by p being of complementary conductivity types to each other, each of said transistors with programmable threshold voltage numbered through p.sup.th having a gate connected to the programming line having the same ordinal number as its own, and each of the remaining transistors with programmable threshold voltage having a gate connected to the programming line having an ordinal number smaller by p than its own;
• a first network connection with intervening nodes of the channels of said first plurality of transistors with fixed threshold voltages and each of said plurality of transistors with programmable threshold voltages and with ordinal number no larger than p.sup.th, for selectively connecting said output logic terminal to said first supply voltage terminal;
• a second network connection with intervening nodes of the channels of said second plurality of transistors with fixed threshold voltages and each of said plurality of transistors with programmable threshold voltages and with ordinal numbers larger than p.sup.th, for selectively connecting said output logic terminal to said second supply voltage terminal, said first and second network connections being duals of each other insofar as impedance and admittance characteristics of their selective connections are concerned;
• and
• means for selectively applying voltages, during such times as programming voltages are applied to said programming lines, to those of said intervening nodes in said first and second network connections as necessary to program the threshold voltages of those transistors with programmable threshold voltages.

A programmable logic array formed from connections of field effect transistors, including field effect transistors with fixed-threshold-voltages and including programmable-threshold-voltage field effect transistors with threshold voltages programmable by application of programming voltages between first ends of their respective channels and their respective gates;

• wherein the channels of the field effect transistors are arranged to provide selectively conductive paths between a logic output terminal of said array and each of two operating supply terminals, for determining the logic output signal at said logic output terminal;
• wherein the gates of the field effect transistors with fixed threshold voltages are connected for receiving logic input signals, at least selected ones of which logic input signals are subject to variation to selectively control the conduction or non-conduction of the channels of the transistors with fixed threshold voltages receiving these signals at their gates;
• wherein the gates of the field effect transistors with programmable threshold voltages are connected to receive programming voltages during programming times, for determining whether their conduction channels are to be substantially non-conductive or substantially fully-conductive during ensuing times of normal operation;
• and
• wherein means are included for selectively connecting one of the ends of the channel of a respective one of each programmable-threshold-voltage transistor, having neither end of its channel continuously connected to one of said operating supply terminals, to a reference voltage for programming voltages, said selective connection being made responsive to a write signal applied simultaneously with said programming voltages.

A programmable logic array formed from connections of field effect transistors, including field effect transistors with fixed-threshold-voltages and including programmable-threshold-voltage field effect transistors with threshold voltages programmable by application of programming voltages between their substrates and their respective gates;

• wherein the channels of the field effect transistors are arranged to provide selectively conductive paths between a logic output terminal of said array and each of two operating supply terminals, for determining the logic output signal at said logic output terminal;
• wherein the gates of the field effect transistors with fixed threshold voltages are connected for receiving logic input signals, at least selected ones of which logic input signals are subject to variation to selectively control the conduction or non-conduction of the channels of the transistors with fixed threshold voltages receiving these signals at their gates;
• wherein the gates of the field effect transistors with programmable threshold voltages are connected to receive programming voltages during programming times, for determining whether their conduction channels are to be substantially non-conductive or substantially fully-conductive during ensuing times of normal operation;
• and
• wherein means are included for selectively connecting one of the ends of the channel of a respective one of each programmable-threshold-voltage transistor, having neither end of its channel continuously connected to one of said operating supply terminals, to a reference voltage for programming voltages, said selective connection being made responsive to a write signal applied simultaneously with said programming voltages.

A programmable logic array connection of switching transistors and programmable switch elements, with first and second supply voltage terminals, a plurality of logic input connections to the gates of said switching transistors, at least one logic output connection with selectively conductive paths to said first and second supply voltage terminals through respective principal conduction paths of ones of said switching transistors and through respective ones of said programmable switch elements, and a plurality of programming lines, said array characterized in that the conductive state of said programmable switch element is not changed responsive to normal logic levels on said logic input connections and further characterized in that to reduce the number of programming lines required for the array at least one of the programmable switch elements essentially consists of:

• a plurality of programmable-threshold-voltage field effect transistors with respective gates and channels, each being of a type with its threshold voltage electrically alterable by application of a programming voltage to its gate;
• and
• means connectng said programmable-threshold-voltage transistors as a programmable logic circuit including
• connection of their channels to provide the programmable switch element path that is conductive or non-conductive and including
• connection of their gates to respective ones of said programming lines, at least one of which is also used in applying programming voltage to another of said programmable switch elements.

A COSMOS logic array having first and second supply voltage terminals;

• a multiplicity m of logic input terminals consecutively ordinally numbered first through m.sup.th ;
• at least one logic output terminal;
• a multiplicity m of n-channel logic FET's associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having channels arranged with intervening nodal connections in a first network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said first supply voltage terminal, and having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own;
• and a multiplicity m of p-channel logic FET's associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own and having channels arranged with intervening nodal connections in a second network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said supply voltage terminal, said first and second networks being duals of each other insofar as impedance and admittance are concerned, said COSMOS logic array modified so as to be programmable by inclusion of programmable-V.sup.T FET's each of a type in which V.sup.T is electrically alterable responsive to voltage applied to its gate, which array is further characterized by:
• the channel of a respective programmable-V.sup.T FET paralleling the channel of each logic FET that is serially connected with another logic FET, the channel of each logic FET that is serially connected with a parallel combination of circuit branches, and each parallel combinations of circuit branches that is serially connected with a logic FET;
• the channel of a respective programmable-V.sub.T FET being interposed in series with the channel of each logic FET that is parallelly connected with another logic FET, the channel of each logic FET that is parallelly connected with a series combination of circuit branches, and each series combination of circuit branches that is parallelly connected with a logic FET;
• and
• means for applying at selected times, programming voltages to the gates of said programmable V.sub.T FET's, and reference voltages to such of said intervening nodal connections as necessary to permit programming of all said programmable-V.sub.T FET's.

A COS/MOS logic array having first and second supply voltage terminals;

• a multiplicity m of logic input terminals consecutively ordinally numbered first through m.sup.th ;
• at least one logic output terminal;
• a multiplicity m of n-channel logic FET's associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having channels arranged with intervening nodal connections in a first network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said first supply voltage terminal, and having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own;
• and a multiplicity m of p-channel logic FET associated with each logic output terminal, being consecutively ordinally numbered first through m.sup.th, having gates connected to the ones of said logic input terminals having the same ordinal numbers as their own and having channels arranged with intervening nodal connections in a second network of series and parallel branches for selectively connecting the logic output terminal associated therewith to said second supply voltage terminal, said first and second networks being duals of each other insofar as impedance and admittance are concerned-- said COS/MOS logic array modified so as to be programmable by inclusion of programmable-V.sub.T FET's each of a type in which V.sub.T is electrically alterable responsive to voltage applied to its gate, which array is further characterized by:
• the channel of a respective programmable-V.sub.T FET parallelling the channel of each logic FET that is serially connected with another logic FET, and the channel of each logic FET that is serially connected with a parallel combination of circuit branches;
• the channel of a respective programmable-V.sub.T FET being interposed in series with the channel of each logic FET that is parallelly connected with another logic FET, and the channel of each logic FET that is parallelly connected with a series combination of circuit branches;
• means connecting the gate of each programmable-V.sub.T FET in series with a logic FET to the same logic input terminal as the gate of that logic FET;
• means connecting the gate of each programmable-V.sub.T FET in parallel with a logic FET to the same logic input terminal at the gate of that logic FET;
• respective switch means parallelling each parallel combination of circuit branches that is serially connected with a logic FET for conducting only when the programmable-V.sub.T FET's in all of the circuit branches in that parallel combination prevent any of them from being conductive, each comprising
• a logic-gate connection of the channels of programmable-V.sub.T FET's with gates connected to respective ones of the logic input terminals connected to the gates of the programmable-V.sub.T FET's in the parallel combination with which that respective switch means is associated;
• switch means interposed in series with each series combination of circuit branches that is parallelly connected with a logic FET for conducting except when the programmable-V.sub.T FET's in all of the circuit branches in that series connection prevent any of them from being non-conductive, each comprising
• a logic-gate connection of the channels of programmable-V.sub.T FET's with gates connected to respective ones of the logic input terminals connected to the gates of programmable-V.sub.T FET's in that series combination with which that respective switch is associated;
• and
• means for applying at selected times, programming voltages to said logic input terminals, and reference voltages to such of said intervening nodal connections as necessary to permit programming of all said programmable-V.sub.T FET's.

A programmable logic gate comprising:

• and second supply voltage terminals;
• a first plurality, n in number, of floating-gate MOSFET's, consecutively ordinally numbered first through n.sup.th, each having a substrate in electrical connection with one of said first and second supply voltage terminals, having a respective principal current conduction path with first and second ends and having a respective control gate electrode;
• a second plurality, n in number, of floating-gate MOSFET's, consecutively ordinally numbered first through n.sup.th, each having a substrate in electrical connection with one of said first and second supply voltage terminals, having a respective principal current conduction path with first and second ends having a respective control gate electrode;
• a plurality, n in number, of further transistors of a first conductivity type, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control electrode;
• a plurality, n in number, of further transistors of a second conductivity type, complementary to said first conductivity type, consecutively ordinally numbered first through n.sup.th, each having a respective principal current conduction path with first and second ends and having a respective control electrode;
• a plurality, n in number, of input terminals, consecutively ordinally numbered first through n.sup.th, each of which input terminals connects to the oontrol electrodes of the pair of said further transistors having ordinal numbers the same as its ordinal number;
• an output terminal;
• series connections between said first supply voltage terminal and said output terminal of each of the principal current conduction paths of said floating-gate MOSFET's of said first plurality with the principal current conduction path of the one of said further transistors of said first conductivity type bearing the same ordinal number;
• parallel connections of each of the principal current conduction paths of said floating-gate MOSFET's of said second plurality with the principal current conduction path of the one of said further transistors of said second conductivity type having the same ordinal number, which parallel connections are serially connected between said output terminal and said supply voltage terminal;
• and
• means selectively applying a respective programming potential between the gate electrode of each of said floating-gate MOSFET's and one of said first and second supply voltage terminals for programming that path to be relatively low resistance or relatively high resistance.