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US 4,064,405 AGranted
Complementary MOS logic circuit
AssigneeWestinghouse Electric Corp.
InventorsJames R. Cricchi, Michael D. Fitzpatrick
Life of this patent
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Abstract
A complementary MOS logic circuit is disclosed. The circuit utilizes two stages with a coupling network comprising a capacitor and a diode used to couple the first stage to the second stage. This results in a circuit with the logic signal coupled to the input being inverted at the output without introducing substantial loss in signal amplitude.
Claims4
An inverter circuit having at least one input terminal and at least one output terminal, comprising:
- a. a first p-channel MOS transistor having its source coupled to said at least one input terminal of said inverter circuit and its gate coupled to a first reference voltage;
- b. a first n-channel MOS transistor having its drain connected to the drain of said first p-channel MOS transistor and its gate and source to a second reference voltage;
- c. a capacitor coupled between the drain and source of said first p-channel MOS transistor;
- d. a second p-channel MOS transistor having its source coupled to a third reference voltage and its gate to said at least one input terminal;
- e. a second n-channel MOS transistor having its drain coupled to the drain of said second p-channel MOS transistor to form said at least one output terminal of said inverter and its gate coupled to the junction formed by connecting the drain of said first p-channel MOS transistor to the drain of said first n-channel MOS transistor;
- and
- f. a diode coupled between the gate and source of said second n-channel MOS transistor.
4 more elements
A non-inverting MOS driver circuit having at least one input terminal and at least one output terminal, comprising:
- a. a first p-channel MOS transistor having its source connected to said at least one input terminal of said driver and its gate to a first reference voltage;
- b. a first n-channel MOS transistor having its drain connected to the drain of said first p-channel MOS transistor to form said at least one output terminal and its gate and source to a second reference voltage;
- c. a capacitor connected between the drain and source of said first p-channel MOS transistor;
- and
- d. a diode coupled between the junction formed by connecting the drain of said first p-channel MOS transistor to the drain of said first n-channel MOS transistor and a third reference voltage.
2 more elements
An MOS inverter having at least one input terminal and at least one output terminal circuit comprising:
- a. a first p-channel MOS transistor having its source connected to said at least one input terminal of said inverter and its gate to a first reference voltage;
- b. a first n-channel MOS transistor having its drain connected to the drain of said first p-channel MOS transistor and its gate and source terminal to a second reference voltage;
- c. a capacitor connected between the drain and source terminals of said first p-channel MOS transistor;
- d. a second p-channel MOS transistor having its source coupled to a third reference voltage, its gate coupled to said at least one input terminal and its drain to said at least one output terminal;
- e. a second n-channel MOS transistor having its drain coupled to the drain of said second p-channel MOS transistor through a first diode and its gate coupled to the junction formed by connecting the drain of said first p-channel MOS transistor to the drain of said first n-channel MOS transistor and its source to a fourth reference voltage;
- f. a second diode coupled between the gate of said second n-channel MOS transistor and said fourth reference voltage;
- g. a third n-channel MOS transistor having its source and gate coupled to a fifth reference voltage and its drain to said at least one output terminal.
4 more elements
An MOS circuit having at least one input terminal and at least one output terminal, comprising:
- a. a first p-channel MOS transistor having its source coupled to at least one input terminal and its gate to a first reference voltage;
- b. a first n-channel MOS transistors having its source and gate coupled to a second reference voltage and its drain to the drain of said first p-channel MOS transistor;
- c. a capacitor coupled between the drain and source of said first p-channel MOS transistor;
- d. a diode coupled between the drain of said first n-channel MOS transistor and a third reference voltage;
- e. a second p-channel MOS transistor and a second n-channel MOS transistor having their respective gates connected in common and to the drain terminals of said first p-channel MOS transistor;
- having their respective source terminals connected in common to form said at least one output terminal and having their respective drain terminals connected to the fourth and fifth reference voltages;
- f. a third n-channel MOS transistor having its source and gate terminals connected in common and to said fifth reference voltage;
- and
- g. a diode coupled between the drain of said third n-channel MOS transistor and the source terminal of said second p-channel transistor.
6 more elements
Dependencies are inferred from the claim text.