Semiconductor device including delay-enhanced inverter circuit and method of forming same

A buffer circuit (buffer) comprising:

• a non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node;
• and
• a delay-enhanced inverter circuit (DE-inverter) having an output at a third node and an input at a fourth node, the DE-inverter including:
• switching-configured (SW) field-effect transistors (FETs) (SW_FETs);
• and
• non-switching-configured (NS) FETs (NS_FETs);
• the NE-inverter including SW_FETs;
• for the NE-inverter and the DE-inverter being considered together, a number of the NS_FETs is greater than zero and a number of the SW_FETs is greater than the number of the NS_FETs;
• a configuration (A) or a configuration (B) being true;
• for the configuration (A):
• the fourth node being the same as the first node and
• for the configuration (B):
• the third node being the same as the second node;
• and
• wherein each of the NS_FETs of the DE-inverter is configured as a capacitor;
• and
• wherein for each of the NS_FETs of the DE-inverter:
• a gate terminal thereof is coupled to one of the third node or the fourth node and is free of having an inverter coupled therebetween, and
• source/drain (S/D) terminals thereof are coupled correspondingly to the fourth node or the third node and are free of having an inverter coupled therebetween.

A buffer circuit (buffer) comprising:

• a non-delay-enhanced inverter circuit (NE-inverter) having an output at a first node and an input at a second node;
• and
• a delay-enhanced inverter circuit (DE-inverter) having an output at a third node and an input at a fourth node, the DE-inverter including:
• switching-configured (SW) field-effect transistors (FETs) (SW_FETs);
• and
• non-switching-configured (NS) FETs (NS_FETs);
• a configuration (A) or a configuration (B) being true;
• for the configuration (A):
• the fourth node being the same as the first node and
• for the configuration (B):
• the third node being the same as the second node;
• and
• wherein the NS_FETs of the DE-inverter are arranged as a capacitive device feedback-coupled between the third node and the fourth node;
• and
• wherein for each of the NS_FETs of the DE-inverter:
• a gate terminal thereof is coupled to one of the third node or the fourth node, and
• source/drain (S/D) terminals thereof are coupled correspondingly to the fourth node or the third node;
• wherein, for one or more first ones of the NS_FETs of the DE-inverter, the gate terminal thereof is coupled to the third node and is free of having an inverter coupled therebetween;
• and
• wherein, for one or more second ones of the NS_FETs of the DE-inverter, the gate terminal thereof is coupled to the fourth node and are free of having an inverter coupled therebetween.