Adaptive dynamic keeper circuit

A dynamic circuit, comprising:

• means for selectively keeping a voltage of a logical state node of the dynamic circuit;
• means for selectively pulling down the voltage of the logical state node during an evaluation phase;
• and
• means for preventing a loss of a logical state of the logical state node by electrically floating a control signal that affects an activation delay associated with the means for selectively keeping in parallel with the means for selectively pulling down the voltage of the logical state node during at least a portion of the evaluation phase.

A method of operating a dynamic circuit, comprising:

• changing a voltage of a logical state node in response to a first leakage current flowing through a first NMOS transistor;
• changing a voltage of a control signal associated with a keeper circuit in response to a second leakage current flowing through a second NMOS transistor in the keeper circuit;
• and
• at least partially activating a PMOS transistor, based on the changed voltage of the control signal, to counteract the change in voltage of the logical state node.

A dynamic circuit, comprising:

• a delay circuit in a global adaptive keeper circuit configured to receive a pre-charge signal and output a delayed version of the pre-charge signal;
• a feed-forward path in the global adaptive keeper circuit configured to receive the pre-charge signal and output an undelayed version of the pre-charge signal;
• a pre-stage circuit comprising a first circuit element, the pre-stage circuit being coupled to the output of the delay circuit and the output of the feed-forward path, the pre-stage circuit configured to output a global control signal;
• a plurality of logical state nodes;
• a plurality of local keeper circuits, each associated with one of the plurality of logical state nodes, each of the plurality of local keeper circuits configured to receive one of a plurality of local control signals, each of the plurality of local control signals configured to be generated based on the global control signal, each of the plurality of local control signals is configured to affect an activation delay associated with one of the plurality of local keeper circuits;
• and
• a plurality of pull down circuits, each associated with one of the plurality of logical state nodes and one of the plurality of local keeper circuits, each of the plurality of pull down circuits comprising a second circuit element;
• wherein, during at least a portion of an evaluation phase of the dynamic circuit, the first circuit element is configured to electrically float each local control signal in parallel with each second circuit element changing a voltage on each associated logical state node of the plurality of logical state nodes.

A design structure embodied in a non-transitory computer readable medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

• a logical state node;
• a keeper circuit coupled to the logical state node, the keeper circuit comprising a first circuit element configured to output a control signal that affects an activation delay associated with the keeper circuit;
• and
• a pull down circuit coupled to the logical state node, the pull down circuit comprising a second circuit element;
• wherein the first circuit element is configured to electrically float the control signal in parallel with the second circuit element changing a voltage on the logical state node during at least a portion of an evaluation phase of a dynamic circuit.

A design structure embodied in a non-transitory computer readable medium for at least one of designing, manufacturing, and testing a design, the design structure comprising:

• a delay circuit in a global adaptive keeper circuit configured to receive a pre-charge signal and output a delayed version of the pre-charge signal;
• a feed-forward path in the global adaptive keeper circuit configured to receive the pre-charge signal and output an undelayed version of the pre-charge signal;
• a pre-stage circuit comprising a first circuit element, the pre-stage circuit being coupled to the output of the delay circuit and the output of the feed-forward path, the pre-stage circuit configured to output a global control signal;
• a plurality of logical state nodes;
• a plurality of local keeper circuits, each associated with one of the plurality of logical state nodes, each of the plurality of local keeper circuits configured to receive one of a plurality of local control signals, each of the plurality of local control signals configured to be generated based on the global control signal, each of the plurality of local control signals configured to affect an activation delay associated with one of the plurality of local keeper circuits;
• and
• a plurality of pull down circuits, each associated with one of the plurality of logical state nodes and one of the plurality of local keeper circuits, each of the plurality of pull down circuits comprising a second circuit element;
• wherein, during at least a portion of an evaluation phase of a dynamic circuit, the first circuit element is configured to electrically float each local control signal in parallel with each second circuit element changing a voltage on each associated logical state node of the plurality of logical state nodes.