G11C 17/123
Comprising cells having several storage transistors connected in series
Official title: {comprising cells having several storage transistors connected in series}
G11C17/123 (Comprising cells having several storage transistors connected in series) appears on 90 US grants and 41 published applications in this corpus.
Search patents in G11C- Granted patents
- 90
- Published applications
- 41
- Assignees
- 51
- Inventors
- 134
- Latest grant
- 6 May 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1977 | 1 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 3 | 0 |
| 1981 | 1 | 0 |
| 1982 | 2 | 0 |
| 1983 | 1 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 3 | 0 |
| 1987 | 4 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 1 | 0 |
| 1991 | 1 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 5 | 0 |
| 1995 | 2 | 0 |
| 1996 | 4 | 0 |
| 1997 | 3 | 0 |
| 1998 | 4 | 0 |
| 1999 | 3 | 0 |
| 2000 | 2 | 0 |
| 2001 | 3 | 1 |
| 2002 | 1 | 0 |
| 2003 | 3 | 2 |
| 2004 | 1 | 2 |
| 2005 | 1 | 3 |
| 2006 | 1 | 1 |
| 2007 | 1 | 0 |
| 2008 | 0 | 2 |
| 2009 | 1 | 1 |
| 2010 | 0 | 0 |
| 2011 | 0 | 1 |
| 2012 | 1 | 0 |
| 2013 | 0 | 0 |
| 2014 | 2 | 0 |
| 2015 | 0 | 2 |
| 2016 | 3 | 3 |
| 2017 | 4 | 4 |
| 2018 | 3 | 1 |
| 2019 | 3 | 4 |
| 2020 | 1 | 3 |
| 2021 | 4 | 1 |
| 2022 | 1 | 2 |
| 2023 | 3 | 3 |
| 2024 | 1 | 2 |
| 2025 | 2 | 3 |
By publication year. Applications have been published since 2001.
Recent patents
- Memory circuit and method of operating same6 May 2025US 12,293,799 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Semiconductor memory devices with different doping types18 Feb 2025US 12,230,681 B2Taiwan Semiconductor Manufacturing Company.Ltd
- High speed differential rom2 Jul 2024US 12,027,229 B2Texas Instruments Incorporated
- Semiconductor memory devices with different doping types26 Dec 2023US 11,856,761 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Memory circuit and method of operating same17 Oct 2023US 11,791,005 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Memory circuit and method of operating same21 Aug 2025US 2025/0266113 A1Taiwan Semiconductor Manufacturing Company.Ltd
- Methods and apparatus to delete and prevent recovery of data stored in a memory array21 Aug 2025US 2025/0266114 A1Intel Corporation
- Semiconductor memory devices with different doping types22 May 2025US 2025/0169142 A1Taiwan Semiconductor Manufacturing Company.Ltd
- High Speed Differential ROM12 Sep 2024US 2024/0304223 A1
- Semiconductor memory devices with different doping types14 Mar 2024US 2024/0090210 A1Taiwan Semiconductor Manufacturing Company.Ltd
Most cited
By later US patents
- NAND stack ROM82US 4,980,861 AMicrochip Technology Incorporated · 1990
- Method of forming a mask programmable read only memory device with multi-level memory cell array56US 5,429,968 ANEC Corporation · 1995
- Single chip MOS/LSI microcomputer with binary timer46US 4,348,743 AMostek Corporation · 1982
- Reference circuit with semiconductor memory array42US 4,648,074 ARCA Corporation · 1987
- X-and-OR memory array35US 4,602,354 ANCR Corporation · 1986