Memory circuit and method of operating same

A memory circuit, comprising:

• a plurality of programming devices, each programming device of the plurality of programming devices comprises a first gate terminal, a second terminal and a third terminal;
• a plurality of fuse elements in a first metal layer, wherein the second terminal of each of the plurality of programming devices is coupled to at least two fuse elements of the plurality of fuse elements;
• a plurality of diodes coupled to the plurality of fuse elements, each diode of the plurality of diodes includes a corresponding via of a plurality of vias;
• a plurality of word lines extending in a first direction, each word line of the plurality of word lines being coupled to at least two programming devices of the plurality of programming devices;
• a plurality of selection devices, wherein each selection device of the plurality of selection devices comprises a second gate terminal, a fourth terminal and a fifth terminal;
• a plurality of bit lines extending in a second direction different from the first direction, the plurality of bit lines being coupled to the plurality of selection devices;
• wherein the second gate terminal of each selection device of the plurality of selection devices is coupled to a corresponding bit line of the plurality of bit lines and is configured to receive a corresponding bit line signal.

A memory circuit, comprising:

• a first programming transistor comprising a first gate terminal coupled to a first word line and configured to receive a first word line signal, and a first drain terminal coupled to a first node;
• a first circuit branch comprising:
• a first diode that corresponds to a first via;
• and
• a first fuse element coupled to the first diode;
• a second circuit branch comprising:
• a second diode that corresponds to a second via;
• and
• a second fuse element coupled to the second diode, wherein a first end of the first circuit branch and the second circuit branch is the first node;
• a first selection transistor comprising a second drain terminal coupled to a second node, wherein the first circuit branch is coupled between the first node and the second node;
• and
• a second selection transistor comprising a third drain terminal coupled to a third node, wherein the second circuit branch is coupled between the first node and the third node, wherein
• the first programming transistor further comprises:
• a first source coupled to a reference voltage supply;
• the first selection transistor further comprises:
• a second source coupled to a voltage supply;
• and
• a second gate coupled to a first bit line and configured to receive a first bit line signal;
• and
• the second selection transistor further comprises:
• a third source coupled to the voltage supply;
• and
• a third gate coupled to a second bit line and configured to receive a second bit line signal.