Single chip MOS/LSI microcomputer with binary timer

A method for producing a time-out signal comprising:

• generating a first load signal;
• a second load signal, a control signal, a clock signal and a read signal;
• receiving a first set of data when the first load signal occurs;
• receiving a second set of data when the second load signal occurs;
• decoding the first set of data to select one of three possible modes of operation;
• decoding the first set of data to select a prescale value when a first or second mode of operation has been selected;
• decoding the second set of data to select a second pulse value;
• producing a first pulse when the first mode of operation has been selected each time the clock signal occurs a number of times determined by the prescale value multiplied by the second pulse value;
• producing a first value when the first mode of operation has been selected and the read signal occurs, said first value being determined by the number of times the clock signal occurs between the occurrences of the first pulse divided by the prescale value;
• producing a second pulse when the second mode of operation has been selected and the control signal occurs each time the clock signal occurs a number of times determined by multiplying the prescale value by the second pulse value;
• producing a second value when the second mode of operation has been selected and the read signal occurs, said second value being determined by the number of times the clock signal occurs between the occurrences of the first pulse divided by the prescale value;
• producing a third pulse when the third mode of operation has been selected each time the control signal occurs a number of times determined by the second pulse value;
• and
• producing a third value when the third mode of operation has been selected, said third value being determined by the number of times the control signal occurs between occurrences of the first pulse.

A count pulse generator circuit comprising:

• external means for producing a clock signal;
• external means for producing an auxiliary control signal;
• a control register for storing and producing a plurality of signals including a stop signal, a pulse width signal, and at least one prescale control signal;
• a control unit which receives the clock signal, the auxiliary control signal and the control register plurality of signals, and which produces
• event count mode count pulses when the stop signal and the prescale control signals are not occurring, each time the auxiliary control signal transitions from a first voltage level to a second voltage level,
• prescale mode count pulses when the stop signal and pulse width signal are not occurring and at least one prescale control signal is occurring, each time a number of clock signals occur, the number being determined by the prescale control signal, and
• pulse width mode count pulses when the stop signal is not occurring, the pulse width signal and at least one prescale control signal are occurring and the auxiliary control signal is at the first voltage level, each time a number of clock signals occur, the number being determined by the prescale control signal.

A count pulse generator circuit operational in a plurality of modes to produce a multiple-purpose pulse output signal in response to at least one prescale signal and a plurality of control signals, including a clock signal, an auxiliary clock signal, first and second start signals and a pulse width signal comprising:

• (a) control circuitry for receiving said control signals and generating a plurality of mode signals representative of one of said plurality of modes;
• (b) prescaler logic circuitry responsive to said mode signals and said at least one prescale signal to generate a timing pulse representative of a predetermined multiple of pulses of said pulse output signal;
• and
• (c) a timing logic unit responsive to said timing pulse to generate one pulse of said multiple-purpose pulse output signal upon counting said predetermined multiple of said timing pulses, said multiple-purpose pulse output signal being representative of:
• (1) time count pulses with the count pulse generator circuit operating in a time count mode, wherein the first start signal is occurring, the pulse width signal is not occurring, and at least one prescale signal is occurring, one of said time count pulses being produced each time a number of clock signals occur, the number being determined by said at least one prescale signal;
• (2) pulse width pulses with the count pulse generator circuit operating in a pulse width mode, wherein the first and second start signals the pulse width signal and at least one prescale signal are occuring, one of said pulse width pulses being produced to measure the width of the second start signal each time a number of clock signals occur, the number being determined by said at least one prescale signal;
• and
• (3) event count pulses with the count pulse generator circuit operating in an event count mode, wherein the first start signal is occurring, and the pulse width signal and all of the prescale signals are not occurring, said event count pulses being produced each time the auxiliary clock signal transitions from a first voltage level to a second voltage level.