G06F 9/30018
Bit or string instructions
Official title: {Bit or string instructions}
G06F9/30018 (Bit or string instructions) appears on 1,062 US grants and 1,038 published applications in this corpus.
Search patents in G06F- Granted patents
- 1,062
- Published applications
- 1,038
- Assignees
- 193
- Inventors
- 1,485
- Latest grant
- 29 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 1 | 0 |
| 1978 | 2 | 0 |
| 1979 | 1 | 0 |
| 1980 | 4 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 3 | 0 |
| 1984 | 3 | 0 |
| 1985 | 3 | 0 |
| 1986 | 4 | 0 |
| 1987 | 0 | 0 |
| 1988 | 1 | 0 |
| 1989 | 3 | 0 |
| 1990 | 9 | 0 |
| 1991 | 4 | 0 |
| 1992 | 7 | 0 |
| 1993 | 7 | 0 |
| 1994 | 10 | 0 |
| 1995 | 11 | 0 |
| 1996 | 6 | 0 |
| 1997 | 10 | 0 |
| 1998 | 26 | 0 |
| 1999 | 18 | 0 |
| 2000 | 19 | 0 |
| 2001 | 10 | 2 |
| 2002 | 12 | 19 |
| 2003 | 17 | 17 |
| 2004 | 9 | 51 |
| 2005 | 15 | 12 |
| 2006 | 15 | 10 |
| 2007 | 16 | 15 |
| 2008 | 21 | 30 |
| 2009 | 16 | 27 |
| 2010 | 25 | 22 |
| 2011 | 18 | 15 |
| 2012 | 25 | 35 |
| 2013 | 28 | 76 |
| 2014 | 28 | 84 |
| 2015 | 40 | 40 |
| 2016 | 75 | 78 |
| 2017 | 91 | 66 |
| 2018 | 49 | 55 |
| 2019 | 63 | 65 |
| 2020 | 59 | 62 |
| 2021 | 67 | 57 |
| 2022 | 45 | 43 |
| 2023 | 53 | 54 |
| 2024 | 46 | 49 |
| 2025 | 39 | 29 |
| 2026 | 24 | 25 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Canceling prefetch of cache blocks based on an address and a bit field29 Sep 2026US 12,748,591 B2SiFive, Inc.
- Method and apparatus for permuting streamed data elements8 Sep 2026US 12,730,758 B2Texas Instruments Incorporated
- Vector friendly instruction format and execution thereof14 Jul 2026US 12,681,729 B2Intel Corporation
- Data interface device of display apparatus23 Jun 2026US 12,663,991 B2LG Display Co., Ltd.
- Atomic update instructions with bit masking9 Jun 2026US 12,650,931 B2Advanced Micro Devices, Inc.
- Computer-implemented method, and device for providing binary instructions3 Sep 2026US 2026/0259734 A1
- Network scheduling method and apparatus20 Aug 2026US 2026/0244444 A1Oriole Networks Ltd.
- Bitmap conversions13 Aug 2026US 2026/0236262 A1Arm Limited
- Register allocation optimization using per-register bin packing6 Aug 2026US 2026/0227979 A1Mellanox Technologies, Ltd.
- Scale instruction for data normalization6 Aug 2026US 2026/0228002 A1QUALCOMM Incorporated
Most cited
By later US patents
- Running-min and running-max instructions for processing vectors using a base value from a key element of an input vector426US 8,417,921 B2Apple Inc. · 2013
- Processing vectors using wrapping minima and maxima instructions in the macroscalar architecture418US 8,555,037 B2Apple Inc. · 2013
- Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags403US 5,226,126 ANexgen Microsystems · 1993
- Sparse convolutional neural network accelerator339US 10,891,538 B2NVIDIA Corporation · 2021
- DRAM with high bandwidth interface that uses packets and arbitration313US 5,778,419 AMicroUnity Systems Engineering, Inc. · 1998