G06F 7/504
In bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations
Official title: in bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other
G06F7/504 (In bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations) appears on 39 US grants and 29 published applications in this corpus.
Search patents in G06F- Granted patents
- 39
- Published applications
- 29
- Assignees
- 34
- Inventors
- 86
- Latest grant
- 9 Jun 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 2 | 0 |
| 1977 | 0 | 0 |
| 1978 | 1 | 0 |
| 1979 | 1 | 0 |
| 1980 | 0 | 0 |
| 1981 | 1 | 0 |
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 0 | 0 |
| 1985 | 0 | 0 |
| 1986 | 1 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 1 | 0 |
| 1991 | 0 | 0 |
| 1992 | 1 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 1 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 2 | 0 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 0 | 1 |
| 2008 | 0 | 0 |
| 2009 | 0 | 3 |
| 2010 | 0 | 1 |
| 2011 | 1 | 0 |
| 2012 | 2 | 0 |
| 2013 | 0 | 1 |
| 2014 | 3 | 1 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 1 | 3 |
| 2018 | 2 | 2 |
| 2019 | 4 | 3 |
| 2020 | 1 | 3 |
| 2021 | 0 | 0 |
| 2022 | 2 | 2 |
| 2023 | 2 | 4 |
| 2024 | 2 | 3 |
| 2025 | 3 | 1 |
| 2026 | 1 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Multiple input serial adder9 Jun 2026US 12,650,809 B2Google Inc.
- Flexible hardware accelerators for masking conversions with a power of two modulus16 Dec 2025US 12,499,277 B2NXP B. V.
- Processing apparatus and method of processing add operation therein23 Sep 2025US 12,423,055 B2Samsung Electronics Co., Ltd.
- Adder circuit using lookup tables11 Mar 2025US 12,248,764 B2Achronix Semiconductor Corporation
- Solid-state imaging device, method for driving solid-state imaging device, and electronic apparatus23 Apr 2024US 11,968,466 B2Brillnics Singapore Pte. Ltd.
- Lower precision operand representation29 Jan 2026US 2026/0029989 A1NVIDIA Corporation
- Adder circuit using lookup tables27 Mar 2025US 2025/0103296 A1Achronix Semiconductor Corporation
- Flexible hardware accelerators for masking conversions with a power of two modulus10 Oct 2024US 2024/0338492 A1NXP B. V.
- Adder circuit using lookup tables22 Aug 2024US 2024/0281212 A1Achronix Semiconductor Corporation
- Method and apparatus for operating memory processor28 Mar 2024US 2024/0103809 A1Samsung Electronics Co., Ltd.
Most cited
By later US patents
- Series type adder for adding plural binary numbers29US 3,941,990 ACompagnie Industrielle des Telecommunications Cit-Alcatel · 1976
- Small, fast CMOS 4-2 carry-save adder cell18US 5,818,747 ASun Microsystems, Inc. · 1998
- Digital function generator10US 3,962,573 ARockwell International Corporation · 1976
- Asynchronous circuit and system9US 4,167,789 AThe Aiken Fund, Inc. · 1979
- Binary calculation circuit8US 4,920,509 AEtat Francais, represente par le ministres Delegue des Postes et Telecommunications (Centre National d'Etudes des Telecommunications) · 1990