Multiple input serial adder
AssigneeGoogle Inc.
InventorHerman Schmit
Life of this patent
Estimating the term…
Abstract
Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.
Claims20
A programmable device, comprising:
- a first processing unit, a second processing unit, and a programmable interconnect, wherein the first processing unit and the second processing unit are connected to the programmable interconnect;
- the first processing unit and the second processing unit each comprising a plurality of full adder circuits configured to collectively receive at least three serial inputs and produce a single serial output that is a summation of the at least three serial inputs, wherein a carried state is maintained among the plurality of full adder circuits;
- the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, wherein the programmable interconnect is configured to receive, from the plurality of full adder circuits of the first processing unit, the single serial output and output, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
A method for operating a programmable device, the programmable device comprising a first processing unit and a second processing unit coupled to a programmable interconnect, the first processing unit and second processing unit each comprising a plurality of full adder circuits and the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, the method comprising:
- collectively receiving, with the plurality of full adder circuits, at least three serial inputs;
- producing, with the plurality of full adder circuits, a single serial output that is a summation of the at least three serial inputs;
- maintaining a carried state among the plurality of full adder circuits;
- receiving, from the plurality of full adder circuits of the first processing unit, the single serial output;
- and
- outputting, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
A non-transitory computer readable medium for storing instructions that, when executed by a programmable device, the programmable device comprising a first processing unit and a second processing unit coupled to a programmable interconnect, the first processing unit and second processing unit each comprising a plurality of full adder circuits and the programmable interconnect being connected between the first processing unit and the second processing unit and comprising a logic gate, causes the programmable device to perform operations comprising:
- collectively receiving, with a plurality of full adder circuits, at least three serial inputs;
- producing, with the plurality of full adder circuits, a single serial output that is a summation of the at least three serial inputs;
- maintaining a carried state among the plurality of full adder circuits;
- receiving, from the plurality of full adder circuits of the first processing unit, the single serial output;
- and
- outputting, to the plurality of full adder circuits of the second processing unit, at least one of the three serial inputs for the second processing unit based on the logic gate.
Dependencies are inferred from the claim text.