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US 12,423,055 B2Granted
Processing apparatus and method of processing add operation therein
AssigneesSamsung Electronics Co., Ltd., Seoul National University R&Db Foundation
InventorsDeokjin Joo, Hossein Moradian Sardroudi, Sujeong Jo, Kiyoung Choi
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Abstract
A method of processing an add operation in a processing apparatus includes acquiring sub-operands from input operands each having an n-bit precision, acquiring intermediate addition results by performing add operations of sub-operands in parallel by using adders, bit-shifting each of the intermediate addition results such that the intermediate addition results correspond to original bit positions in the input operands, and outputting a final addition result of the add operations of the input operands based on the bit-shifted intermediate addition results.
Claims11
A processor-implemented method of a processor including a plurality of adder circuitries, the method comprising:
- generating a plurality of sub-operands, respectively corresponding to bit values of bit sections of a plurality of operands of an input feature map of a neural network, having a first pixel configuration, by dividing the plurality of operands into the bit sections each having a predetermined bit size, wherein each of the plurality of operands has an n-bit precision, and n is a natural number;
- generating respective intermediate bit results by operating the plurality of adder circuitries in parallel through each of the plurality of adder circuitries being provided respective multiple sub-operands of the plurality of sub-operands;
- generating an output feature map, having a second pixel configuration different from the first pixel configuration, by combining bit-shifted intermediate bit results that result from respective bit-shiftings of the respective intermediate bit results based on respective bit positions in the plurality of operands, such that the combined bit-shifted intermediate bit results correspond to a summation result for the plurality of operands;
- and
- dependent on a performed determination that there is a zero-bit section, among the bit sections, in which a corresponding sub-operand has a zero-value:
- in the operating of the plurality of adder circuitries in parallel, controlling a corresponding one adder circuitry, of the plurality of adder circuitries, allocated to the zero-bit section to not operate with respect to the corresponding sub-operand, thereby skipping performance of an add operation with respect to the corresponding sub-operand;
- and
- controlling the corresponding one adder circuitry to operate with respect to an other operand, other than the plurality of operands, to decrease an idling of the corresponding one adder circuitry.
5 more elements
A processing apparatus comprising:
- one or more memories storing instructions;
- and
- one or more processors configured to execute the instructions, wherein the execution of the instructions configures the one or more processors to:
- generate a plurality of sub-operands, respectively corresponding to bit values of bit sections of a plurality of operands of an input feature map of a neural network, having a first pixel configuration, by dividing the plurality of operands into the bit sections each having a certain bit size, wherein each of the plurality of operands has an n-bit precision, and n is a natural number;
- generate respective intermediate bit results by operating a plurality of adder circuitries in parallel through each of the plurality of adder circuitries being provided different respective multiple sub-operands of the plurality of sub-operands;
- generate an output feature map, having a second pixel configuration different from the first pixel configuration, by combining bit-shifted intermediate bit results that result from respective bit-shiftings of the respective intermediate bit results based on respective bit positions in the plurality of operands, such that the combined bit-shifted intermediate bit results correspond to a summation result for the plurality of operands;
- and
- dependent on a performed determination that there is a zero-bit section, among the bit sections, in which a corresponding sub-operand has a zero-value:
- in the operating of the plurality of adder circuitries in parallel, control a corresponding one adder circuitry, of the plurality of adder circuitries, allocated to the zero-bit section to not operate with respect to the corresponding sub-operand, thereby skipping performance of an add operation with respect to the corresponding sub-operand;
- and
- control the corresponding one adder circuitry to operate with respect to an other operand, other than the plurality of operands, to decrease an idling of the corresponding one adder circuitry.
8 more elements
Dependencies are inferred from the claim text.