Flexible hardware accelerators for masking conversions with a power of two modulus

A hardware converter configured to convert d arithmetic shares of x to d Boolean shares of x using a modulus of 2k, where x has k bits, the hardware converter comprising:

• a first plurality of hardware addition layers, each layer comprising:
• a second plurality of secure bit adders and a second plurality of multiplexers, wherein each of the secure bit adders are configured to add a first input and a second input and produce an output having N shares, wherein N is an integer greater than one,
• the first input of each secure bit adder is N shares, wherein the first N/2 of the shares of the first input are zero shares,
• the second input of each secure bit adder is N shares, wherein the last N/2 of the shares of the second input are zero shares,
• the inputs to each of the secure bit adders of the second plurality of secure bit adders of a first layer include a kth bit of the d arithmetic shares of x,
• the inputs to each of the secure bit adders of the second plurality of secure bit adders of remaining layers include the output of a previous layer,
• each of the secure adders includes a carry bit input and a carry bit output,
• the multiplexers receive the carry bit output from a respective associated secure bit adder and a fixed bit value,
• a respective output of each of the multiplexers is connected to the carry bit input of the respective associated secure bit adder, and
• a first multiplexer of the second plurality of multiplexers outputs the fixed bit value for the first bit of the d shares of x and the remaining multiplexers of the second plurality of multiplexers output the carry output from a prior bit for a second to kth bits.

A hardware converter configured to convert d Boolean shares of x to d arithmetic shares of x using a modulus of 2k, where x has k bits, comprising:

• a random number generator configured to generate d−1 random arithmetic shares of x;
• a secure hardware arithmetic shares to Boolean shares converter (SecA2B) configured to receive the generated d−1 random arithmetic shares and a dth share that is zero and to produce SecA2B Boolean output shares using a modulus of 2k,
• a secure hardware subtractor configured to receive the SecA2B Boolean output shares from the SecA2B and to securely subtract the SecA2B Boolean output shares of the SecA2B from the d Boolean shares of x producing subtracted output shares;
• a refresh circuit configured to receive the subtracted output shares from the secure hardware subtractor, and to refresh the subtracted output shares from the secure hardware subtractor producing refreshed output shares;
• and
• an unmask circuit configured to receive the refreshed output shares from the refresh circuit and to combine the refreshed output shares of the refresh circuit to produce the dth arithmetic share of x.