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US 3,941,990 AGranted
Series type adder for adding plural binary numbers
AssigneeCompagnie Industrielle des Telecommunications Cit-Alcatel
InventorJean Rabasse
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AssigneeCompagnie Industrielle des Telecommunications Cit-Alcatel
InventorJean Rabasse
Estimating the term…
Series type adder receiving numbers having different polarities, constituted by elementary series type adders combining the positive input numbers and the true complements of the negative input numbers to work out the sum .SIGMA. thereof, characterized in that it comprises means for calculating the sum S of the sign bits of the negative input numbers and effecting the storing thereof in a memory, means for extracting the exceeding number D appearing at the end of the calculating of .SIGMA., means for comparing S and D in order to determine the sign of .SIGMA. existing in a memory register and in order to control the transferring thereof in true form, in an output, preceded by its sign.
A series type adder for adding during successive clock periods a plurality of binary numbers of any polarity received in serial form and having a sign bit as the first bit thereof by adding positive numbers and true complement of negative numbers, comprising a plurality of detection circuits for storing the respective sign bits of said binary numbers, gate means responsive to said detection circuits for forming the true complements of the negative binary numbers, adding means including a plurality of elementary series type adders for adding said positive numbers and the true complements of negative numbers, delay means for re-injecting carry-over bits and bits representing the sum of carry-over bits coupled from outputs of said adding means to inputs thereof, memory means connected to said adding means for storing the output thereof representing the addition of said binary numbers, logic directing means responsive to the outputs of one of said elementary series type adders for providing during one clock instant of an adding cycle a sum output representing the sum of the sign bits of the negative numbers and during another clock instant of said adding cycle the carry-over output of said adding means, auxiliary memory means connected to said logic directing means for storing said sum output thereof, circuit means, included within said logic directing means, for providing the carry-over output from said logic directing means, comparator means for comparing the output of said auxiliary memory means to the output of said circuit means during a final clock instant of said adding cycle, and transfer means connected to said comparator means for enabling the contents of said memory means to be preceded by a sign bit determined by the output of said comparator means.
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
In bit-serial fashion, i.e. having a single digit-handling circuit treating all denominations after each other: for multiple operands
Computing and data processing
Term ended 2 Mar 1993 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
The present invention comes within the branch of series type binary adders effecting the sum of binary elements applied to its inputs.
It is a known practice to constitute an elementary series type binary adder, effecting the adding of two numbers emitted simultaneously in the form of two pulse trains having increasing weights, by a logic circuit having two inputs receiving respectively the two pulse trains and a third input on which the outgoing carry-over is re-injected after having been delayed by a pulse period. An elementary series type adder thus has two outputs: a "carry-over" output for a carry-over to be re-injected at the carry-over input and a "sum" output on which is sent out the result of the addition effected.
It is thus possible to produce a series type adder effecting the adding of more than two numbers starting with several elementary series type adders having three inputs and two outputs each. These elementary series type adders combine in threes, at their inputs, the bits taken from among the bits having the same weight of the input binary numbers to be added, the carry-over bits suitably delayed by one order in relation to the bits which gave rise to them sent out at the carry-over outputs, the part sum bits sent out on the sum outputs of the respective adders except for one of them which will send out the successive bits of the complete addition.
Other characteristics and advantages of the present invention will become apparent from the description of an embodiment given with reference to the accompanying drawing, in which:
FIG. 1 shows a known diagram of a series type adder receiving four input figures; that series type adder has been described hereinbelow;
FIG. 2 shows the diagram of a series type adder according to the invention.
In FIG. 2, the case in which three numbers having any polarity are to be added has been taken into consideration.
Each of the numbers to be added designated by N1, N2 and N3 is in binary form; the first binary element is the sign bit; the following binary elements are the bits which characterize it; these latter bits are sent out in an order of increasing power. The binary numbers N1, N2 and N3 are applied simultaneously to the series type adder.
The series type adder comprises three elementary series type adders 4, 5 and 6, each having three inputs respectively 41 to 43, 51 to 53, 61 to 63, a sum output 44, 54, 64 and a carry-over output 45, 55, 65. The numbers N1, N2 and N3 are applied to a first input of three logic gates of the "exclusive OR" type, 71, 73, and 75, which transmit them respectively to the inputs 41, 42 and 51 of the elementary series type adders 4 and 5. On their respective second inputs, the three exclusive OR gates receive the outputs of three flip-flops 72, 74 and 76 respectively controlled, throughout the duration of the operation for the adding of N1, N2 and N3, by the sign bit assigned to the number applied to the corresponding exclusive OR gate.