US 5,818,747 A · Small, fast CMOS 4-2 carry-save adder cell

Abstract

A CMOS 4-2 carry-save adder cell implementation. A XNOR gate is used in the computation of SUM and CARRY. By using an XNOR gate, there are no possible input permutations which will cause any output in the SUM logic to be driven by two P-channel devices in series. The final XOR function needed to compute the SUM output is performed by a 2-to-1 multiplexor and two inverters. The maximum resistance from input to output of the 2-to-1 multiplexor is relatively low, and the worst case is when the CIN input drives through the transmission gate. The input capacitances are very low. The maximum load driven by the output is low because the output never drives through the drains of any transistors. Instead, the output drives only the gates of four transistors to implement the XOR function. A single 8-transistor complex gate and an inverter are used to calculate COUT. The transistors in the complex gate can be made relatively small, thus minimizing the input capacitance. A complex gate is used to implement the logic function .about.((IN0 & IN1)+(IN2 & IN3)). The output of this complex gate is double buffered using two inverters. Minimum size transistors for the complex gate further minimize the input capacitances and reduce the area needed to lay out the gate. All the outputs are driven by final inverters to provide strong, clean outputs.

Claims18

Dependent claims

A method of providing a CMOS 4-2 carry-save adder cell, taking inputs IN0, IN1, IN2, IN3, and CIN, and computing outputs SUM, CARRY, and COUT, the method comprising the steps of:

providing a first six-transistor XOR circuit taking IN0 and IN1 as inputs for computing a first intermediate value;
providing a second six-transistor XOR circuit taking IN2 and IN3 as inputs for computing a second intermediate value;
providing a six-transistor XNOR circuit taking the first and second intermediate values as inputs for computing a third intermediate value;
providing a first inverter taking the third intermediate value as input for computing a fourth intermediate value;
providing a second inverter taking CIN as input for computing a fifth intermediate value;
providing a first four-transistor 2-to-1 multiplexor circuit taking CIN and the third, fourth, and fifth intermediate values as inputs for computing a sixth intermediate value, such that the sixth intermediate value is equal to CIN if the third intermediate value is low or is equal to the fifth intermediate value if the third intermediate value is high;
providing a third inverter taking the sixth intermediate value as input for computing the SUM output;
providing a CARRY subcalculation circuit taking IN0, IN1, IN2, and IN3 as inputs for computing a seventh intermediate value;
providing a second four-transistor 2-to-1 multiplexor circuit taking the third, fourth, fifth, and seventh intermediate values as inputs for computing an eighth intermediate value;
providing a fourth inverter taking the eighth intermediate value as input for computing the CARRY output;
and
providing a COUT calculation circuit taking IN0, IN1, IN2, and IN3 as inputs for computing the COUT output.

9 more elements

A method of performing a carry-save addition, taking inputs IN0, IN1, IN2, IN3, and CIN, and computing outputs SUM, CARRY, and COUT, the method comprising the steps of:

computing a first intermediate value using a first six-transistor XOR circuit taking IN0 and IN1 as inputs;
computing a second intermediate value using a second six-transistor XOR circuit taking IN2 and IN3 as inputs;
computing a third intermediate value using a six-transistor XNOR circuit taking the first and second intermediate values as inputs;
computing a fourth intermediate value using a first inverter taking the third intermediate value as input;
computing a fifth intermediate value using a second inverter taking CIN as input;
computing a sixth intermediate value, such that the sixth intermediate value is equal to CIN if the third intermediate value is low or is equal to the fifth intermediate value if the third intermediate value is high using a first four-transistor 2-to-1 multiplexor circuit taking CIN and the third, fourth, and fifth intermediate values as inputs;
computing the SUM output using a third inverter taking the sixth intermediate value as input;
computing a seventh intermediate value using a CARRY subcalculation circuit taking IN0, IN1, IN2, and IN3 as inputs;
computing an eighth intermediate value using a second four-transistor 2-to-1 multiplexor circuit taking the third, fourth, fifth, and seventh intermediate values as inputs;
computing the CARRY output using a fourth inverter taking the eighth intermediate value as input;
and
computing the COUT output using a COUT calculation circuit taking IN0, IN1, IN2, and IN3 as inputs.

9 more elements

A CMOS 4-2 carry-save adder cell, taking inputs IN0, IN1, IN2, IN3, and CIN, and computing outputs SUM, CARRY, and COUT, the adder cell comprising:

a first six-transistor XOR circuit taking IN0 and IN1 as inputs for computing a first intermediate value;
a second six-transistor XOR circuit taking IN2 and IN3 as inputs for computing a second intermediate value;
a six-transistor XNOR circuit taking the first and second intermediate values as inputs for computing a third intermediate value;
a first inverter taking the third intermediate value as input for computing a fourth intermediate value;
a second inverter taking CIN as input for computing a fifth intermediate value;
a first four-transistor 2-to-1 multiplexor circuit taking CIN and the third, fourth, and fifth intermediate values as inputs for computing a sixth intermediate value, such that the sixth intermediate value is equal to CIN if the third intermediate value is low or is equal to the fifth intermediate value if the third intermediate value is high;
a third inverter taking the sixth intermediate value as input for computing the SUM output;
a CARRY subcalculation circuit taking IN0, IN1, IN2, and IN3 as inputs for computing a seventh intermediate value;
a second four-transistor 2-to-1 multiplexor circuit taking the third, fourth, fifth, and seventh intermediate values as inputs for computing an eighth intermediate value;
a fourth inverter taking the eighth intermediate value as input for computing the CARRY output;
and
a COUT calculation circuit taking IN0 IN1, IN2, and IN3 as inputs for computing the COUT output.

9 more elements

Dependencies are inferred from the claim text.

Small, fast CMOS 4-2 carry-save adder cell

Life of this patent

Small, fast CMOS 4-2 carry-save adder cell

Life of this patent

Abstract

Claims18