G06F 7/49957
Implementation of ieee-754 standard
Official title: {Implementation of IEEE-754 Standard}
G06F7/49957 (Implementation of ieee-754 standard) appears on 145 US grants and 65 published applications in this corpus.
Search patents in G06F- Granted patents
- 145
- Published applications
- 65
- Assignees
- 45
- Inventors
- 219
- Latest grant
- 22 Sep 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1982 | 1 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 3 | 0 |
| 1990 | 2 | 0 |
| 1991 | 4 | 0 |
| 1992 | 1 | 0 |
| 1993 | 5 | 0 |
| 1994 | 6 | 0 |
| 1995 | 3 | 0 |
| 1996 | 4 | 0 |
| 1997 | 16 | 0 |
| 1998 | 13 | 0 |
| 1999 | 5 | 0 |
| 2000 | 4 | 0 |
| 2001 | 8 | 0 |
| 2002 | 3 | 2 |
| 2003 | 2 | 3 |
| 2004 | 3 | 3 |
| 2005 | 2 | 1 |
| 2006 | 3 | 0 |
| 2007 | 0 | 2 |
| 2008 | 1 | 4 |
| 2009 | 0 | 0 |
| 2010 | 1 | 1 |
| 2011 | 2 | 1 |
| 2012 | 4 | 4 |
| 2013 | 2 | 2 |
| 2014 | 2 | 1 |
| 2015 | 4 | 2 |
| 2016 | 3 | 9 |
| 2017 | 8 | 4 |
| 2018 | 8 | 2 |
| 2019 | 3 | 8 |
| 2020 | 4 | 3 |
| 2021 | 2 | 3 |
| 2022 | 2 | 0 |
| 2023 | 3 | 4 |
| 2024 | 0 | 1 |
| 2025 | 4 | 4 |
| 2026 | 2 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Floating point fused multiply add with merged 2's complement and rounding22 Sep 2026US 12,743,251 B2Texas Instruments Incorporated
- System and method for efficient even polynomial evaluation using transformation-enhanced fused multiply-add operations18 Aug 2026US 12,710,925 B1Next Silicon Ltd
- Dynamic directional rounding14 Oct 2025US 12,443,394 B2NVIDIA Corporation
- Exact versus inexact decimal floating-point numbers and computation system15 Apr 2025US 12,277,404 B2King Fahd University of Petroleum and Minerals
- Decimal floating-point instruction in a round-for-reround mode11 Feb 2025US 12,223,290 B2International Business Machines Corporation
- Dynamic directional rounding15 Jan 2026US 2026/0017017 A1NVIDIA Corporation
- Method and system for decimal floating-point computation26 Jun 2025US 2025/0208831 A1King Fahd University of Petroleum and Minerals
- Methods and systems for quantization of large language models19 Jun 2025US 2025/0200277 A1
- Deep neural network architecture using piecewise linear approximation17 Apr 2025US 2025/0124266 A1Intel Corporation
- Optimized multiply-accumulate operator for ai calculations30 Jan 2025US 2025/0036362 A1
Most cited
By later US patents
- Vector register addressing125US 6,332,186 B1Arm Limited · 2001
- Numeric data processor119US 4,338,675 AIntel Corporation · 1982
- Fraction bus for use in a numeric data processor100US 4,484,259 AIntel Corporation · 1984
- Method and system of rounding for division or square root: eliminating remainder calculation98US 5,764,555 AInternational Business Machines Corporation · 1998
- Methods and apparatus for performing division and square root computations in a computer96US 5,404,324 AHewlett-Packard Company · 1995