US 6,332,186 B1 · Vector register addressing

Abstract

A floating point unit 26 is provided with a register bank 38 comprising 32 registers that may be used as either vector registers V or scalar registers S. Data values are transferred between memory 30 and the registers within the register bank 38 using contiguous block memory access instructions. Vector processing instructions specify a sequence of processing operations to be performed upon data values within a sequence of registers. The register address is incremented between each operation by an amount controlled by a stride value. Accordingly, the register address can be incremented by values such as 0, 1, 2 or 4 between each iteration. This provides a mechanism for retaining block memory access instructions to contiguous memory addresses whilst supporting vector matrix and/or complex operations in which the data values needed for each iteration are not adjacent to one another in the memory 30.

Claims12

Dependent claims

Apparatus for data processing, said apparatus comprising:

a register bank having a plurality of registers for holding data values to be manipulated, each of said registers having a register address;
a memory accessing circuit responsive to at least one block memory access instruction for performing memory accesses between a plurality of contiguously addressed memory locations within a memory and a plurality of contiguously addressed registers within said register bank;
and
an instruction decoder responsive to at least one vector processing instruction for sequentially executing a data processing operation a plurality of times upon operands stored within a predetermined sequence of said registers;
wherein
between each execution of said data processing operation, said instruction decoder is responsive to a programmable stride value to increment a register address of a register storing an operand used in said data processing operation by an amount specified by said stride value.

3 more elements

Dependencies are inferred from the claim text.

Vector register addressing

Life of this patent

Vector register addressing

Life of this patent

Abstract

Claims12