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US 12,743,251 B2Granted
Floating point fused multiply add with merged 2's complement and rounding
AssigneeTexas Instruments Incorporated
InventorGarrett Joseph Lies
Life of this patent
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Abstract
A method includes receiving an unrounded mantissa value and a round bit associated with the unrounded mantissa value. The method also includes receiving a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation. The method includes incrementing the unrounded mantissa value to provide an incremented value. The unrounded mantissa value is a non-incremented value. The method further includes providing one of the incremented value or non-incremented value as a rounded mantissa value responsive to the 2's complement signal.
Claims18
A method, comprising:
- generating a sum by an adder;
- incrementing, by a first incrementor, a first set of data to provide an incremented first set of data;
- selecting, by a first multiplexor, one of the first set of data and the incremented first set of data as a set of selected bits based on a specified precision type;
- generating, by the adder, an unrounded mantissa value comprising the sum and the set of selected bits based on the specified precision type;
- receiving the unrounded mantissa value and a round bit associated with the unrounded mantissa value;
- receiving a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation;
- normalizing the unrounded mantissa value to generate a normalized unrounded mantissa value, the normalizing in parallel with generating:
- a sticky bit associated with the unrounded mantissa value, wherein the sticky bit comprises an OR reduction of bits in the unrounded value that are less-significant than the round bit and a previous sticky bit;
- and a ones bit associated with the unrounded mantissa value, wherein the ones bit comprises an AND reduction of the bits in the unrounded mantissa value that are less-significant than the round bit and a previous ones bit;
- incrementing, by a second incrementor, the normalized unrounded mantissa value to provide an incremented value, wherein the normalized unrounded mantissa value is a non-incremented value;
- and
- providing, by a second multiplexor, one of the incremented value and a non-incremented value as a rounded mantissa value responsive to the 2's complement signal and to the round bit.
9 more elements
A system, comprising:
- a normalizer configured to:
- receive an unnormalized, unrounded mantissa value;
- provide, responsive to the unnormalized, unrounded mantissa value and a shift signal, a normalized, unrounded mantissa value, and provide, responsive to the unnormalized, unrounded mantissa value, a round bit;
- provide a sticky bit that comprises an OR reduction of bits in the unnormalized, unrounded mantissa value that are less-significant than the round bit based on an inverse of the shift signal;
- and
- provide a ones bit that comprises an AND reduction of bits in the unnormalized, unrounded mantissa value that are less-significant than the round bit based on the shift signal;
- and
- a rounding unit coupled to the normalizer, the rounding unit comprising:
- an incrementor configured to increment the normalized, unrounded mantissa value to provide an incremented value, wherein the normalized, unrounded mantissa value is a non-incremented value;
- a rounding select circuit configured to:
- receive the round bit;
- receive a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation;
- and
- provide a rounding output responsive to the 2's complement signal;
- and
- a multiplexor (mux) coupled to the incrementor and the rounding select circuit, the mux configured to:
- receive the incremented value and the non-incremented value as inputs;
- receive the rounding output as a control signal;
- and
- provide one of the incremented value or non-incremented value as a rounded mantissa value responsive to the rounding output.
17 more elements
A method, comprising:
- receiving, by a normalizer, an unnormalized, unrounded mantissa value;
- providing, responsive to the unnormalized, unrounded mantissa value and a shift signal, a normalized, unrounded mantissa value, and provide, responsive to the unnormalized, unrounded mantissa value, a round bit;
- providing a sticky bit that comprises an OR reduction of bits in the unnormalized, unrounded mantissa value that are less-significant than the round bit based on an inverse of the shift signal;
- providing a ones bit that comprises an AND reduction of bits in the unnormalized, unrounded mantissa value that are less-significant than the round bit based on the shift signal;
- incrementing, by an incrementor, the normalized, unrounded mantissa value to provide an incremented value, wherein the normalized, unrounded mantissa value is a non-incremented value;
- receiving, by a rounding select circuit, the round bit;
- receiving a 2's complement signal that indicates whether the unrounded mantissa value results from a 1's complement operation;
- providing a rounding output responsive to the 2's complement signal;
- receiving, by a multiplexer, the incremented value and the non-incremented value as inputs;
- receiving the rounding output as a control signal;
- and
- providing one of the incremented value or non-incremented value as a rounded mantissa value responsive to the rounding output.
9 more elements
Dependencies are inferred from the claim text.