Method and system of rounding for division or square root: eliminating remainder calculation
AssigneeInternational Business Machines Corporation
InventorsThomas Joseph McPherson, Eric Mark Schwarz
Life of this patent
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Abstract
A method and system which provides exactly rounded division and square root results for a designated rounding mode independently of a remainder, or equivalent calculation of the relationship between the remainder and zero, for predetermined combinations of the rounding mode and the guard digit of an estimate that has several more bits of precision than the exactly rounded result, and has an error tolerance magnitude less than the weight of the least significant bit of the estimate. The estimate is generated in accordance with a quadratically converging division or square root algorithm. The method and system is described in connection with IEEE 754-1985 and IBM S/390 binary floating point architectures.
Claims21
A system that provides, for a designated rounding mode, an exactly rounded result having a predetermined number of bits for a square root or a division operation, the exactly rounded result representing rounding in the designated rounding mode of an infinitely precise result to the division or square root operation, the system comprising:
- a first storage unit that contains information indicative of the designated rounding mode;
- a second storage unit that contains an approximate result to the division or square root operation, the approximate result having G more bits of precision than the exactly rounded result to the division or square root operation, and having an error magnitude less than the weight of the least significant bit of the approximate result, the least significant G bits of the approximate result called a guard digit, the approximate result exclusive of the guard digit called a truncated approximate result;
- a remainder circuit that provides a remainder output signal representative of a difference between the infinitely precise result and the approximate result to the division or square root operation;
- a selection signal generating circuit that generates a selection signal, wherein for a predetermined combination of said guard digit and the information indicative of the designated rounding mode said selection signal is generated independently of said remainder output signal, and wherein for another predetermined combination of said guard digit and the information indicative of the designated rounding mode said selection signal is generated in response to the information indicative of the designated rounding mode and the remainder output signal;
- and
- a rounding circuit that provides the exactly rounded result in response to said selection signal, the exactly rounded result being generated from the approximate result and having a value dependent on the selection signal.
A system that provides, for a designated rounding mode, an exactly rounded result having a predetermined number of bits for a square root or a division operation, the system comprising:
- an approximation unit that calculates an approximate result having "G" more bits of precision than the desired exactly rounded result to the division or square root operation, and having an error magnitude less than the weight of the least significant bit of the approximate result;
- and
- a processor that exactly rounds the approximate result independent of a computation indicative of a remainder in predetermined cases characterized by the designated rounding mode and the least significant bit of the approximate result.
A system for providing an N bit exactly rounded result, according to a designated rounding mode, for a square root or a division operation, the exactly rounded result representing rounding in the designated rounding mode of an infinitely precise result to the division or square root operation, N having a nonzero positive value, the system comprising:
- means for generating an N+G bit estimate to the infinitely precise result of the square root or division operation, said estimate having an error difference from said infinitely precise result with a magnitude less than the weight of the least significant (N+G)th bit, the least significant G bits referred to as the guard digit;
- and
- means for providing the exactly rounded result according to the designated rounding mode and the value of the guard digit, independently of a remainder signal representative of a difference between the infinitely precise result and the estimate to the division or square root operation, for a predetermined combination of the guard digit and the designated rounding mode.
A method of providing an N bit exactly rounded result, according to a designated rounding mode, for a square root or a division operation, the exactly rounded result representing rounding in the designated rounding mode of an infinitely precise result to the division or square root operation, N having a nonzero positive value, the method comprising the steps of:
- generating an N+G bit estimate signal to the infinitely precise result of the square root or division operation, said estimate having an error difference from said infinitely precise result with a magnitude less than the weight of the least significant (N+G)th bit, the least significant G bits referred to as the guard digit;
- and
- providing the exactly rounded result according to the designated rounding mode and the value of the guard digit, independently of a remainder signal representative of a difference between the infinitely precise result and the estimate signal to the division or square root operation, for a predetermined combination of the guard digit and the designated rounding mode.
Dependencies are inferred from the claim text.