System and method for efficient even polynomial evaluation using transformation-enhanced fused multiply-add operations
AssigneeNext Silicon Ltd
InventorOded Margalit
Life of this patent
Estimating the term…
Loading patent…
AssigneeNext Silicon Ltd
InventorOded Margalit
Estimating the term…
A hardware processing system for evaluating degree-2n even polynomials comprises a plurality of fused multiply-add (FMA) units fabricated on a semiconductor substrate, each having dedicated multiplication circuitry and addition circuitry operating in parallel. A scheduling controller with dependency analysis circuitry orchestrates polynomial evaluation by allocating FMA units and configuring hardware interconnect circuitry comprising signal paths, multiplexers, and routing logic. A configuration memory stores pre-computed transformation constants and restructured polynomial coefficients as fixed hardware parameters. The system modifies conventional processor datapath architecture by routing the transformation constant from configuration memory to the addition input of a first FMA unit during squaring operations, productively utilizing addition circuitry that would conventionally receive hardwired zero values. The transformation constant restructures computational dependencies, enabling the scheduling controller to dispatch parallel FMA operations to separate units during the same clock cycle.
A hardware processing system comprising:
A computer-implemented method for evaluating even polynomials in a hardware computing system, comprising:
Dependencies are inferred from the claim text.