US 5,404,324 A · Methods and apparatus for performing division and square root computations in a computer

Abstract

An apparatus for performing floating-point division and square root computations according to an IEEE rounding standard includes input data alignment circuitry, core iteration circuitry, remainder compare circuitry, and round and select circuitry. The core iteration circuitry includes digit selector circuitry; remainder registers; quotient logic circuitry; remainder formation circuitry; and quotient registers for storing the quotient Q, incremented quotient Q+1, and decremented quotient Q-1. The remainder formation circuitry produces sum and carry bits of the P.sub.j+1 term, which are in turn fed back to the partial remainder registers and used in subsequent iterations. The quotient logic circuitry builds the quotient Q and maintains the respective quotient Q, Q+1, Q-1 registers. The outputs of these registers are fed back to the quotient logic circuitry for use in subsequent iterations. The remainder compare circuitry comprises a remainder comparator and a logic circuit. The remainder comparator receives the sum and carry bits for the P.sub.j+1 terms and outputs the "Sign" and "Zero" bits. These bits are received by the logic circuit along with a rounding mode signal, which is indicative of the selected rounding mode, e.g., shifted or normalized round to nearest, round to zero, or round to infinity. The logic circuit outputs a round select signal that selects a quotient select signal for selecting, as the final rounded quotient, the output of one of the quotient registers Q, Q+1, or Q-1. The round and select circuitry includes a round block for positive remainders and a round block for negative remainders.

Claims15

Dependent claims

An apparatus for performing floating-point digit-by-digit division in a computer, comprising:

(a) input data alignment means for aligning a dividend operand and a divisor operand to place said operands in a prescribed format;
(b) digit selector logic for selecting quotient digits q.sub.j+1 to be used in iteratively constructing a quotient Q;
(c) remainder formation logic for generating a division partial remainder P.sub.j+1 in accordance with the following formula for division:
P.sub.j+1 =rP.sub.j -q.sub.j+1 D,
where "j" is an index representing iterations employed in constructing said quotient, "P.sub.j " represents the remainder at the j-th iteration, "r" represents the radix of the number system employed to represent numbers in the computer, and "D" represents the divisor;
(d) quotient logic for iteratively constructing said quotient Q in accordance with the formula
Q.sub.j+1 =Q.sub.j +r.sup.-(j+1) q.sub.j+1,
where "Q.sub.j " represents the quotient Q at the j-th iteration and for decrementing and incrementing said quotient Q to obtain a decremented quotient Q-1 and an incremented quotient Q+1;
(e) a Q register for storing the quotient Q, a QM register for storing the decremented quotient Q-1, and a QP register for storing the incremented quotient Q+1;
(f) remainder compare logic for receiving a rounding mode signal indicative of a selected one of a plurality of prescribed rounding modes, determining whether said partial remainder P.sub.j+1 is zero and whether said partial remainder is less than zero, and outputting a round select signal;
and
(g) round and select logic for selecting, as a final rounded quotient, one of Q, Q-1, and Q+1 on the basis of the last quotient digit q.sub.j+1 and said round select signal.

9 more elements

An apparatus for performing floating-point digit-by-digit division of a dividend operand by a divisor operand, comprising:

(a) digit selector means for selecting quotient digits q.sub.j+1 to be used in iteratively constructing a quotient Q;
(b) remainder formation means for generating a division partial remainder P.sub.j+1 ;
(c) quotient means for iteratively constructing a quotient Q, and for decrementing and incrementing said quotient Q to obtain a decremented quotient Q-1 and an incremented quotient Q+1;
(d) remainder compare means for receiving a rounding mode signal indicative of a selected one of a plurality of prescribed rounding modes, determining whether said partial remainder P.sub.j+1 is zero and whether said partial remainder is less than zero, and outputting a round select signal;
and
(e) round and select means for selecting, as a final rounded quotient, one of Q, Q-1, and Q+1 on the basis of a last quotient digit q.sub.j+1 and said round select signal;
wherein delays introduced by the rounding process number approximately log.sub.2 n+K.sub.2, where K.sub.2 is a constant and represents the number of bits in the quotient.

4 more elements

Dependencies are inferred from the claim text.

Methods and apparatus for performing division and square root computations in a computer

Life of this patent

Methods and apparatus for performing division and square root computations in a computer

Life of this patent

Abstract

Claims15