G06F 5/08
Having a sequence of storage locations, the intermediate ones not being accessible
Official title: having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register {(G06F5/065 takes precedence; shift registers per se G11C19/00)}
G06F5/08 (Having a sequence of storage locations, the intermediate ones not being accessible) appears on 177 US grants and 110 published applications in this corpus.
Search patents in G06F- Granted patents
- 177
- Published applications
- 110
- Assignees
- 101
- Inventors
- 310
- Latest grant
- 11 Nov 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1976 | 5 | 0 |
| 1977 | 3 | 0 |
| 1978 | 2 | 0 |
| 1979 | 4 | 0 |
| 1980 | 0 | 0 |
| 1981 | 2 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 1 | 0 |
| 1986 | 1 | 0 |
| 1987 | 2 | 0 |
| 1988 | 1 | 0 |
| 1989 | 6 | 0 |
| 1990 | 2 | 0 |
| 1991 | 3 | 0 |
| 1992 | 2 | 0 |
| 1993 | 3 | 0 |
| 1994 | 2 | 0 |
| 1995 | 2 | 0 |
| 1996 | 3 | 0 |
| 1997 | 4 | 0 |
| 1998 | 4 | 0 |
| 1999 | 4 | 0 |
| 2000 | 6 | 0 |
| 2001 | 1 | 1 |
| 2002 | 3 | 1 |
| 2003 | 0 | 3 |
| 2004 | 6 | 6 |
| 2005 | 6 | 5 |
| 2006 | 8 | 3 |
| 2007 | 2 | 3 |
| 2008 | 4 | 2 |
| 2009 | 4 | 3 |
| 2010 | 1 | 3 |
| 2011 | 4 | 3 |
| 2012 | 4 | 5 |
| 2013 | 2 | 4 |
| 2014 | 5 | 7 |
| 2015 | 7 | 5 |
| 2016 | 6 | 5 |
| 2017 | 6 | 6 |
| 2018 | 5 | 2 |
| 2019 | 9 | 10 |
| 2020 | 7 | 9 |
| 2021 | 5 | 3 |
| 2022 | 4 | 3 |
| 2023 | 6 | 6 |
| 2024 | 6 | 3 |
| 2025 | 3 | 4 |
| 2026 | 0 | 5 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Subgroups
Granted patents
Recent patents
- Associatively indexed circular buffer11 Nov 2025US 12,468,530 B2Marvell Asia Pte Ltd
- Compiler-based input synchronization for processor with variant stage latencies29 Jul 2025US 12,373,182 B2SambaNova Systems, Inc.
- Vector computation unit in a neural network processor15 Apr 2025US 12,277,499 B2Google Inc.
- Waveform generator12 Nov 2024US 12,140,714 B2STMicroelectronics S,r.l.
- Asynchronous finite state machine output masking with customizable topology5 Nov 2024US 12,135,575 B2STMicroelectronics International N. V.
- Alignment in hardware accelerators28 May 2026US 2026/0147536 A1OpenAI OpCo, LLC
- Data encoding without overhead19 Mar 2026US 2026/0081810 A1Koninklijke Philips N. V.
- Associatively indexed circular buffer29 Jan 2026US 2026/0030024 A1Marvell Asia Pte Ltd
- Multiplexor for a processing unit of memory22 Jan 2026US 2026/0023528 A1Micron Technology, Inc.
- Multiplexor placement for implementing a processing unit in memory22 Jan 2026US 2026/0024576 A1Micron Technology, Inc.
Most cited
By later US patents
- Interface circuit having a shift register inserted between a data transmission unit and a data reception unit49US 4,649,512 ANEC Corporation · 1987
- Interpreting I/O operation requests from pageable guests without host intervention49US 7,941,799 B2International Business Machines Corporation · 2011
- System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic41US 6,308,229 B1Theseus Logic, Inc. · 2001
- FIFO memory with decreased fall-through delay40US 4,833,655 AWang Laboratories, Inc. · 1989
- High speed, very large (8 megabyte) first in/first out buffer memory (FIFO)38US 4,809,232 AThe United States of America as represented by the United States Department of Energy · 1989