System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic

A First-In-First-Out (FIFO) circuit comprising:

• a plurality of registers that operate asynchronously aligned to define a data path from a first register of said plurality of registers to a last register of said plurality of registers;
• said first register capable of connecting to an at least partially synchronous upstream circuit;
• and
• said last register capable of connecting to an at least partially synchronous downstream circuit;
• said upstream circuit comprising a clocked binary logic to a null convention logic interface, comprising:
• a first storage element capable of receiving clocked binary logic signals;
• a plurality of parallel second storage elements connected to the first storage element through dual data paths, one of said dual data paths including an inverter;
• logic elements in each of the dual data paths through which data from the first storage element passes in response to said first register requesting data and a control signal;
• outputs of the second storage elements being connected to a threshold gate, said control signal being at least partially derived from an output of said threshold gate;
• and
• output lines capable of passing asynchronous signals from said second storage elements to said first register;
• wherein said last register will output information in a FIFO format consistent with the input of the information into said first register.

A First-In-First-Out (FIFO) circuit comprising:

• a plurality of registers that operate asynchronously aligned to define a data path from a first register of said plurality of registers to a last register of said plurality of registers;
• said first register capable of connecting to an at least partially synchronous upstream circuit;
• and
• said last register capable of connecting to an at least partially synchronous downstream circuit;
• said downstream circuit comprising a null convention logic to a clocked binary logic interface, comprising;
• a first latch having an input that receives a signal from said last register;
• a second latch having an output that passes said signal as a clocked binary signal;
• and
• a switch, disposed between an output of said first latch and an input of said second latch, being in an open state in response to a request from another downstream circuit;
• wherein said last register will output information in a FIFO format consistent with the input of the information into said first register.

A First-In-First-Out (FIFO) circuit comprising:

• a clocked splitting circuit capable of splitting an original data stream into a plurality of separate data streams;
• a plurality of clocked boolean logic to null convention logic converters;
• a plurality of FIFO buffers that operate asynchronously;
• a plurality of null convention logic to clocked boolean logic converters;
• a clocked combining circuit capable of combining distinct data streams into a common data stream;
• and
• a plurality of data paths, each defined by said splitting circuit, a respective one of said plurality of clocked boolean logic to null convention logic converters, at least one respective one of said plurality of asynchronous dual rail FIFO buffers, a respective one of said plurality of null convention logic to clocked boolean logic converters, and said synchronous combining circuit.

A method of passing data between clocked logic circuits, comprising:

• converting synchronous boolean logic signals into asynchronous signals comprising alternating waves of meaningful and non-meaningful signals;
• propagating the asynchronous signals through a plurality of registers that operate asynchronously;
• holding, at each of the registers, one of a meaningful signal and a non-meaningful signal;
• indicating, from each of the registers, a readiness to receive a non-meaningful signal in response to the respective register holding a meaningful signal, and readiness to receive a meaningful signal in response to the respective register holding a non-meaningful signal;
• and
• outputting the asynchronous signals to a second interface circuit in response to a downstream boolean circuit indicating readiness to receive data.

A method for asynchronously transferring data in a First-In-First-Out (FIFO) format, comprising:

• receiving binary logic signals timed by a first clock signal;
• converting the binary logic signals into asynchronous signals in null convention logic format interspersed with NULL levels;
• storing the asynchronous signals in FIFO format;
• and
• converting the asynchronous signals in FIFO format into binary logic signals in FIFO format timed by a second clock signal.

A method of converting a data signal of a first clock domain to a second clocked signal of a second clock domain, comprising:

• receiving a first clocked data stream;
• splitting the first clocked data stream into a plurality of first data substreams;
• converting each first data substream to a respective asynchronous signal;
• storing each respective asynchronous signal into a respective asynchronous FIFO buffer;
• converting each respective asynchronous signal into a respective second data substream of a second clock domain;
• and
• combining each of said second data substreams to form a second clocked data stream.