Asynchronous finite state machine output masking with customizable topology

An asynchronous finite state machine, comprising:

• an input net;
• a core receiving inputs provided by the input net and comprising:
• a plurality of state cells including at least a source state cell configured to generate a source state signal and a destination state cell linked to the source state cell through an arc circuit, the destination state cell configured to generate a destination state signal;
• wherein the source state cell is configured to cause a transition in the source state signal in response to a transition in the destination state signal communicated to the source state cell through a feedback path;
• wherein a state overlap time is an elapsed time between transition of the destination state signal and transition of the source state signal in response thereto;
• and
• a delay circuit within the feedback path;
• and
• an output net receiving inputs from the core, the output net comprising:
• a balanced logic tree receiving inputs, including the destination state signal, from the core;
• and
• an additional logic tree cascaded with the balanced logic tree to form an unbalanced logic tree such that at least one input to the additional logic tree is provided by output from the balanced logic tree, another input to the additional logic tree receiving the source state signal from the core;
• wherein a tree propagation time is an elapsed time between receipt of a transition in the destination state signal by the balanced logic tree and a resulting transition of the output from the balanced logic tree provided to the additional logic tree;
• and
• wherein the delay circuit inserts a delay to the feedback path that causes the state overlap time to be greater than the tree propagation time.