Compiler-based input synchronization for processor with variant stage latencies

A reconfigurable processor, comprising:

• an array of compute units on an integrated circuit substrate, each of the compute units comprising a pipeline of a plurality of arithmetic logic units and a plurality of registers arranged in a plurality of stages, and the registers chained together to propagate data between the stages of the plurality of stages;
• and
• runtime logic configuring the array of compute units with configuration data that
• causes first and second producer stages in a given compute unit to execute first and second data processing operations and produce first and second outputs at first and second stage latencies;
• and
• synchronizes consumption of the first and second outputs by a consumer stage in the given compute unit for execution of a third data processing operation by introducing a register storage delay that compensates for a difference between the first and second stage latencies using at least one register of the given compute unit.

A system, comprising:

• a processor having computing units on an integrated circuit substrate, each computing unit of the computing units having multiple hardware stages, the processor configured to map a program across multiple hardware stages with each hardware stage executing a corresponding operation of the program at a different stage latency dependent on an operation type and an operand format;
• runtime logic configuring the compute units with configuration data that
• causes first and second producer hardware stages in a given compute unit to execute first and second data processing operations and produce first and second outputs at first and second stage latencies;
• and
• synchronizes consumption of the first and second outputs by a consumer hardware stage in the given compute unit for execution of a third data processing operation by introducing a register storage delay that compensates for a difference between the first and second stage latencies using a hardware storage of the compute unit.