US 4,833,655 A · FIFO memory with decreased fall-through delay

Abstract

A first-in, first out data memory minimizes fall-through delay. The FIFO memory has a plurality of cascaded register stages arranged in sections, with the input of each section selectively coupled to a bypass bus. Data is introduced on the bypass bus, and control logic writes the data into the section nearest the output which is currently not full. The individual register stages are self-clocked, so that data is then shifted toward the output through any vacant registers. In another aspect, the register stages are arranged in sections of different length, with the shortes section closest to the output and the longest section closest to the input. Decreased fall-through delay is achieved by minimizing the length of the FIFO buffer actually traversed by the data while insuring that the order of the data remains unchanged.

Claims10

Dependent claims

A first in, first out data memory comprising

a plurality of shift register sections, sequentially arranged and coupled for cascade operation, each of said sections comprising a predetermined number of shift register stages;
each section having a smaller number of stages than the one preceding it;
input means coupled to each section for writing data thereto;
output means coupled to the last of said sections for reading date from said data memory;
means for shifting data written to any one of said stages sequentially through the stages to the last of the stages which does not presently contain data;
and
means for selectively writing data directly into the section nearest the output means which is not presently full of data for the purpose of decreasing fall-through delay time.

4 more elements

A first in, first out data memory comprising

a plurality of shift register sections, sequentially arranged and coupled for cascade operation, each of said sections comprising a predetermined number of shift register stages;
each section having a small number of register stages than the one preceding it;
input means coupled to each section for writing data thereto;
a bypass bus, selectively coupled to the input means of each section, through which data is introduced;
output means, coupled to the last of said sections, for reading data from said data memory;
first status means, associated with each of said register stages, for indicating an empty data condition for that stage and a full data condition for the preceding register stage;
first control logic means, associated with each of said register stages and responsive to said first status means, to advance said data from the preceding register stage to the present register stage;
second status means, coupled to each of said sections, for indicating either a full or not full data condition for that section;
and
second control logic means, coupled to each of said sections and responsive to said second status means, for selecting which of said sections is to receive data from said bypass bus;
whereby data input to said data memory is always written into the section nearest the output means which presently indicates a not full data condition for the purpose of decreasing fall-through delay time.

8 more elements

Dependencies are inferred from the claim text.

FIFO memory with decreased fall-through delay

Life of this patent

FIFO memory with decreased fall-through delay

Life of this patent

Abstract

Claims10