G06F 2212/652
Page size control
G06F2212/652 (Page size control) appears on 408 US grants and 356 published applications in this corpus.
Search patents in G06F- Granted patents
- 408
- Published applications
- 356
- Assignees
- 114
- Inventors
- 787
- Latest grant
- 28 Apr 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1987 | 1 | 0 |
| 1988 | 1 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 2 | 0 |
| 1992 | 1 | 0 |
| 1993 | 2 | 0 |
| 1994 | 3 | 0 |
| 1995 | 10 | 0 |
| 1996 | 7 | 0 |
| 1997 | 2 | 0 |
| 1998 | 14 | 0 |
| 1999 | 10 | 0 |
| 2000 | 9 | 0 |
| 2001 | 8 | 0 |
| 2002 | 9 | 3 |
| 2003 | 8 | 7 |
| 2004 | 6 | 6 |
| 2005 | 3 | 11 |
| 2006 | 7 | 16 |
| 2007 | 8 | 12 |
| 2008 | 12 | 8 |
| 2009 | 11 | 11 |
| 2010 | 13 | 11 |
| 2011 | 10 | 11 |
| 2012 | 12 | 13 |
| 2013 | 14 | 15 |
| 2014 | 17 | 15 |
| 2015 | 17 | 16 |
| 2016 | 14 | 10 |
| 2017 | 12 | 15 |
| 2018 | 9 | 17 |
| 2019 | 24 | 40 |
| 2020 | 36 | 23 |
| 2021 | 25 | 12 |
| 2022 | 12 | 28 |
| 2023 | 11 | 14 |
| 2024 | 23 | 17 |
| 2025 | 19 | 18 |
| 2026 | 5 | 7 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Method, system, and apparatus for page sizing extension28 Apr 2026US 12,613,807 B2UNM Rainforest Innovations
- Counter-based prefetch management for memory14 Apr 2026US 12,602,327 B2
- Systems and methods for updating memory side caches in a multi-GPU configuration24 Feb 2026US 12,561,276 B2Intel Corporation
- Memory controller management techniques for managing data transfer for memory access operations24 Feb 2026US 12,561,277 B2Intel Corporation
- Multi-tile memory management17 Feb 2026US 12,554,674 B2Intel Corporation
- Method, system, and apparatus for page sizing extension3 Sep 2026US 2026/0259833 A1UNM Rainforest Innovations
- Memory controller management techniques30 Jul 2026US 2026/0220078 A1Intel Corporation
- Systems and methods for updating memory side caches in a multi-gpu configuration23 Jul 2026US 2026/0211839 A1Intel Corporation
- Memory controller management techniques23 Jul 2026US 2026/0211840 A1Intel Corporation
- Dynamic control of error management and signaling2 Jul 2026US 2026/0186975 A1Lodestar Licensing Group LLC
Most cited
By later US patents
- Virtual memory computer apparatus and address translation mechanism employing hashing scheme and page frame descriptor that support multiple page sizes158US 5,446,854 ASun Microsystems, Inc. · 1995
- Method, system and computer program product for dynamically allocating large memory pages of different sizes157US 6,182,089 B2Silicon Graphics, Inc. · 2001
- Physical address size selection and page size selection in an address translator151US 5,617,554 AIntel Corporation · 1997
- Processor with an addressable address translation buffer operative in associative and non-associative modes125US 5,835,963 AHitachi, Ltd. · 1998
- Virtual address to physical address translation cache that supports multiple page sizes119US 5,479,627 ASun Microsystems, Inc. · 1995