Multi-tile memory management

A system comprising:

• an interconnect to a system interface;
• and
• a multi-die graphics processing unit coupled with the interconnect, the multi-die graphics processing unit comprising:
• an interposer;
• a first chiplet coupled with the interposer, the first chiplet including a graphics processing circuitry and a switched interconnect network coupled with the graphics processing circuitry;
• cache circuitry coupled with the graphics processing circuitry via the switched interconnect network;
• and
• a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache, wherein the memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing circuitry and a chiplet interface.