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US 12,613,807 B2Granted
Method, system, and apparatus for page sizing extension
AssigneeUNM Rainforest Innovations
InventorsEdward Grochowski, Julio Gago, Roger Gramunt, Roger Espasa, Rolf Kassa
Life of this patent
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Abstract
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.
Claims20
A processor comprising:
- a register to store a base address of a first translation table of a plurality of translation tables, the plurality of translation tables to map virtual memory to physical memory;
- a translation table walker to look up a first entry in the first translation table, a second entry in a second translation table, a third entry in a third translation table, and a fourth entry in a fourth translation table, wherein
- the first entry is to include a first physical address of the second translation table, the second entry is to include a second physical address of the third translation table, the third entry is to include a third physical address of the fourth translation table, and the fourth entry is to include a fourth physical address of a page, and
- the fourth entry is also to include controls, the controls including a bit being set to indicate that the page is a pre-selected size and may be built from pages that are of a size different from the pre-selected size, the bit indicating the presence of the page of the pre-selected size in memory beginning at a page base address indicated by an address field, the bit indicating that a page table entry should be cached using a translation lookaside buffer (TLB) associated with the pre-selected size, the bit being reset indicating the page table entry may be cached using a TLB associated with a different size,
- wherein performing a page table walk includes determining a page size of the page table entry based on the bit.
2 more elements
A method comprising:
- looking up, by a translation table walker, a first entry in a first translation table of a plurality of translation tables, the plurality of translation tables to map virtual memory to physical memory, wherein a base address of the first translation table is stored in a register and the first entry includes a first physical address of a second translation table;
- looking up, by the translation table walker, a second entry in the second translation table of the plurality of translation tables, wherein the second entry includes a second physical address of a third translation table;
- looking up, by the translation table walker, a third entry in the third translation table of the plurality of translation tables, wherein the third entry includes a third physical address of a fourth translation table;
- looking up, by the translation table walker, a fourth entry in the fourth translation table of the plurality of translation tables, wherein the fourth entry includes a fourth physical address of a page and the fourth entry also includes controls including a bit to be set to indicate that the is a pre-selected size and may be built from pages that are of a size different from the pre-selected size, the bit indicating the presence of the page of the pre-selected size in memory beginning at a page base address indicated by an address field, the bit indicating that a page table entry should be cached using a translation lookaside buffer (TLB) associated with the pre-selected size, the bit being reset indicating the page table entry may be using a TLB associated with a different size,
- wherein performing a page table walk includes determining a page size of the page table entry based on the bit.
2 more elements
A system comprising:
- a physical memory;
- and
- a processor comprising:
- a register to store a base address of a first translation table of a plurality of translation tables, the plurality of translation tables to map virtual memory to the physical memory;
- a translation table walker to look up a first entry in the first translation table, a second entry in a second translation table, a third entry in a third translation table, and a fourth entry in a fourth translation table, wherein
- the first entry is to include a first physical address of the second translation table, the second entry is to include a second physical address of the third translation table, the third entry is to include a third physical address of the fourth translation table, and the fourth entry is to include a fourth physical address of a page, and
- the fourth entry is also to include controls, the controls to include a bit to be set to indicate that the page is a pre-selected size and may be built from pages that are of a size different from the pre-selected size, the bit indicating the presence of the page of the pre-selected size in memory beginning at a page base address indicated by an address field, the bit indicating that a page table entry should be using a translation lookaside buffer (TLB) associated with the pre-selected size, the bit being reset indicating the page table entry may be using a TLB associated with a different size,
- wherein performing a page table walk includes determining a page size of the page table entry based on the bit.
5 more elements
Dependencies are inferred from the claim text.