Physical address size selection and page size selection in an address translator

An address translator for physical memory, said address translator translating a linear address having no more than N bits into a physical address, said address translator comprising:

• memory size selection means for selecting a physical address size to be a first address size having no more than said number of N bits or a second address size designated by a number greater than said N bits;
• one or more page directories, each having a group of page directory entries, said linear address having a page directory field for selecting a page directory entry;
• a plurality of page tables, each having a group of page table entries, said linear address having a format, said format selected from a plurality of predetermined formats, at least one of said plurality of predetermined formats having a page table field for selecting a page table entry;
• means, responsive to said memory size selection means, for formatting the page table entries to a first page table entry size if the first address size has been selected or to a second page table entry size if the second address size has been selected, said second page table entry size being larger than the first page table entry size;
• and
• paging means for simultaneously supporting paging using at least a first and a second page frame size while one or more control bits are in a first state, said paging means supporting paging using only one page frame size while said one or more control bits are in a second state.

A method for use by a processor to translate a linear address having a size of no more than N bits into a physical address having a size of a first address size designated by a number no more than N bits or a second address size designated by a number greater than N bits, said method using a plurality of tables including one or more page directories with page directory entries and at least one page table with page table entries, said method comprising the computer implemented steps of:

• said processor altering a physical address mode indicator, said physical address mode indicator identifying said physical address size to be the first address size or the second address size;
• if the first address size has been selected, then said processor setting the page directory entries and the page table entries to a first entry size;
• if the second address size has been selected, then said processor setting the page directory entries and the page table entries to a second entry size that is larger than the first entry size;
• and
• said processor translating said linear address into said physical address using those of said plurality of tables having a corresponding field in said linear address, said processor simultaneously supporting paging using at least a first and a second page size while one or more control bits are in a first state, said processor supporting paging using only one page size while said one or more control bits are in a second state.

A computer system comprising:

• a processor including:
• a control unit having stored therein an indication in one of a plurality of states, and
• a paging unit coupled to said control unit to receive said indication, said paging unit simultaneously supporting paging using at least a first and a second page frame size while said indication is in a first of said plurality of states, said paging unit supporting paging using only one page frame size while said indication is in a second of said plurality of states;
• and
• a memory coupled to said processor, said memory having stored therein a plurality of page tables for use by said paging unit to simultaneously support paging using at least said first and said second page frame sizes.

An address translation apparatus for use by a processor to translate a linear address having no more than N bits into a physical address, said linear address having a first field and a second field, said address translation apparatus comprising:

• means for executing one or more instructions on said processor to store a physical address mode indicator, said physical address mode indicator identifying which of a first physical address size and a second physical address size will be utilized by said processor, said first physical address size having no more than 2.sup.N locations that can be addressed, said second physical address size having more than 2.sup.N locations that can be addressed;
• means for formatting page directory entries in one or more page directories and page table entries in a plurality of page tables to be compatible with the physical address size identified by said physical address mode indicator;
• means for applying both said first field and a value to select a page directory entry as a selected page directory entry if said first physical address size is identified by said physical address mode indicator, wherein said first field is applied as a directory field and said value is stored in said processor;
• means for applying both a first portion of said first field and said value to select one of a plurality of directory pointer table entries as a selected directory pointer table entry, selecting one of a plurality of page directories as said selected page directory using said selected directory pointer table entry, and applying a second portion of said first field as a directory field to select a page directory entry as a selected page directory entry from said selected page directory if said second physical address size is identified by said physical address mode indicator, wherein said first portion of said first field is applied as a pointer field;
• and
• means for applying said selected page directory entry and said second field to provide a physical address, wherein at least a first and a second page frame size is supported while a set of control bits is in a first state and only one page frame size is supported while said set of control bits is in a second state.