G06F 2212/1024
Latency reduction
G06F2212/1024 (Latency reduction) appears on 3,958 US grants and 4,504 published applications in this corpus.
Search patents in G06F- Granted patents
- 3,958
- Published applications
- 4,504
- Assignees
- 568
- Inventors
- 7,057
- Latest grant
- 6 Oct 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 0 | 0 |
| 1987 | 0 | 0 |
| 1988 | 0 | 0 |
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 2 | 0 |
| 1998 | 0 | 0 |
| 1999 | 2 | 0 |
| 2000 | 2 | 0 |
| 2001 | 3 | 0 |
| 2002 | 2 | 0 |
| 2003 | 0 | 2 |
| 2004 | 2 | 1 |
| 2005 | 1 | 4 |
| 2006 | 4 | 4 |
| 2007 | 1 | 3 |
| 2008 | 4 | 3 |
| 2009 | 3 | 16 |
| 2010 | 2 | 7 |
| 2011 | 6 | 18 |
| 2012 | 10 | 15 |
| 2013 | 22 | 46 |
| 2014 | 41 | 94 |
| 2015 | 66 | 163 |
| 2016 | 152 | 212 |
| 2017 | 218 | 351 |
| 2018 | 292 | 422 |
| 2019 | 364 | 430 |
| 2020 | 472 | 521 |
| 2021 | 427 | 328 |
| 2022 | 401 | 437 |
| 2023 | 415 | 462 |
| 2024 | 450 | 437 |
| 2025 | 401 | 342 |
| 2026 | 190 | 186 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- System and method for handling cache updates6 Oct 2026US 12,754,847 B2Ampere Computing LLC
- Canceling prefetch of cache blocks based on an address and a bit field29 Sep 2026US 12,748,591 B2SiFive, Inc.
- Method of forming ferroelectric chiplet in a multi-dimensional packaging with I/O switch embedded in a substrate or interposer25 Aug 2026US 12,717,479 B2Kepler Computing Inc.
- Non-deterministic memory protocol25 Aug 2026US 12,717,481 B2
- Stashing specific merge end trigger for stashing merged data25 Aug 2026US 12,717,580 B2Arm Limited
- Methods and apparatus for eviction in dual datapath victim cache system1 Oct 2026US 2026/0300187 A1
- Memory expansion method and related device24 Sep 2026US 2026/0288629 A1Huawei Technologies Co., Ltd.
- Methods and apparatus to facilitate read-modify-write support in a victim cache17 Sep 2026US 2026/0277825 A1
- Memory controller and storage device including the same10 Sep 2026US 2026/0267565 A1SK hynix Inc.
- Load store bank aware thread scheduling techniques27 Aug 2026US 2026/0252384 A1Intel Corporation
Most cited
By later US patents
- Reducing metadata in a write-anywhere storage system331US 9,116,819 B2DataDirect Networks, Inc. · 2015
- Multi-array operation support and related devices, systems and software224US 9,229,854 B1Radian Memory Systems, Inc. · 2016
- Three level memory hierarchy using write and share flags144US 4,442,487 AInternational Business Machines Corporation · 1984
- Prefetching data for peripheral component interconnect devices132US 6,792,496 B2Intel Corporation · 2004
- Multi-array operation support and related devices, systems and software125US 9,710,377 B1Radian Memory Systems, Inc. · 2017