Multi-array operation support and related devices, systems and software

An integrated circuit, comprising:

• a memory controller to control the performance of memory transactions directed to multiple arrays of flash memory;
• and
• interface circuitry sufficient to exchange information with a host and with the multiple arrays of flash memory;
• wherein the memory controller includes logic to, via the interface circuitry, receive one or more requests from the host relating to a transaction operand in the multiple arrays of flash memory, the one or more requests each specifying an address for each of the multiple arrays of flash memory, and to control satisfaction of the one or more requests by the multiple arrays of flash memory;
• wherein the memory controller is configured to preserve page addressing specified by each of the one or more requests relative to any erase unit (EU) position within flash memory, such that any address translation performed by the memory controller for any one of the multiple arrays of flash memory is limited to translating EU location within the one or more arrays of flash memory;
• wherein each array of the multiple arrays comprises memory cells characterized by a program-erase asymmetry, in which each EU of the multiple arrays comprises multiple smallest-size, independently programmable units (PUs) of the multiple arrays;
• and
• wherein
• the integrated circuit further comprises storage to store information for each respective PU of each EU of the multiple arrays that indicates whether data stored in the respective PU is stale,
• the memory controller is capable of commanding erase of any EU of the multiple arrays for which information in the storage indicates that all constituent PUs are stale, and
• the logic of the memory controller is further to receive a multiplane deallocate command from the at least one host, the deallocate command sufficient to identify associated physical addresses in respective ones of the multiple arrays, the logic to mark the information in the storage for each PU corresponding to the associated physical address locations identified by the deallocate command to indicate a stale status.

An integrated circuit comprising:

• an interface to communicate with a host;
• an interface to communicate with a memory device, the memory device of a technology characterized by a program-erase asymmetry, in which each smallest-size, independently erasable unit (EU) in the memory device comprises multiple smallest-size, independently programmable units (PUs) of the memory device;
• a memory controller having logic to receive a multi-plane transaction request from the host, and to control performance of the multi-plane transaction request by the memory device;
• wherein the multi-plane transaction request specifies a base address location, requests read data from an address in a first plane of the memory device dependent on the base address, requests read data from an address in a second plane of the multi-plane memory device dependent on the base address, and is embodied in the form of one or more commands;
• and
• wherein the memory controller is configured to preserve PU addressing specified by each of the one or more requests relative to any EU position within the memory device, such that any address translation performed by the memory controller for one of the first plane or the second plane is limited to translating EU location within at least one of the first plane or the second plane in the memory device.

A method of managing data access directed to multiple arrays of flash memory, the method comprising:

• receiving one or more write requests from a host, the one or more write requests specifying write of respective data into one or more addresses in respective arrays of the flash memory;
• transmitting at least one write request to the multiple arrays of the flash memory, the at least one write request specifying a physical address responsive to each address received from the host;
• receiving one or more read requests from the host that command read of the respective data from the respective arrays flash memory;
• and
• transmitting at least one read request to the multiple arrays of the flash memory, the at least one read request specifying a physical address responsive to each address received from the host;
• wherein said method further comprises preserving page addressing specified by each of the one or more write requests and each of the one or more read requests relative to any erase unit (EU) position within flash memory, such that any address translation for any one of the multiple arrays of flash memory responsive to a received host request is limited to translating EU location within the one or more arrays of flash memory.