Three level memory hierarchy using write and share flags

In a multiprocessor system, including a three level memory hierarchy, the combination comprising:

• at least first and second processors which are operative with said memory hierarchy;
• a main memory at memory level three, in which a plurality of sets of information, with each set of information being comprised of subsets of said information, are stored at addressable locations, with each set of information including a WRITE flag and a SHARE flag, with the state of the WRITE flag determining if the set of information is writeable or read only by a processor, and the state of the SHARE flag determining if each set of information is shareable or non-shareable by all processors, with each flag being established in a predetermined state;
• at least first and second private caches at memory level two connected to said main memory, and which are operative exclusively with said at least first and second processors respectively, in which a given number of sets of information previously transferred from main memory are stored;
• a first shared cache at memory level two connected to said main memory, which is operative with each of said at least first and second processors, in which a given number of sets of information previously transferred from main memory are stored;
• at least third and fourth private caches at memory level one, which are connected to and operative with said at least first and second private caches, respectively, and exclusively with said at least first and second processors, respectively, in which a given number of said subsets of said sets of information previously transferred from said at least first and second private caches, respectively are stored;
• a second shared cache at memory level one, which is connected to and operative with said first shared cache and each of said at least first and second processors, in which a given number of said subsets of said sets of information previously transferred from said first shared cache are stored;
• and
• a system control element which is connected to and operative with said main memory at memory level three and said at least first and second private caches and said first shared cache at memory level two, and which is operative in response to a given processor interrogating its associated private caches and shared caches at memory levels one and two to access a subset of a selected set of information which is found to be not stored therein, with said system control element checking the state of said WRITE and SHARE flags of said selected set of information in said main memory, for transferring said selected set of information to said first shared cache at memory level two when said WRITE and SHARE flags are each in a given predetermined state indicative of said selected set of information being both writeable and shareable, and for transferring said selected set of information to one of said first and second private caches at memory level two when at least one of said WRITE and SHARE flags are not in said given predetermined state, which is indicative of said selected set of information not being both writeable and shareable.

In a multiprocessor system, including a three level memory hierarchy, the combination comprising:

• n processors, where n is an integer.gtoreq.2;
• a main memory at memory level three, in which pages of information, each page comprised of a plurality of lines, are stored at addressable locations, with each page including a WRITE flag and a SHARE flag, with the state of the WRITE flag determining if each line in the page is writeable or read only by a processor, and the state of the SHARE flag determining if each line in the page is shareable or non-shareable by all processors, with each flag being set in a predetermined state;
• a first shared cache at memory level two, which is operative with each of said n processors, including means for transferring a page of information from main memory to said first shared cache when the WRITE and SHARE flags are each in a given predetermined state, indicative of said page of information being both writeable and shareable;
• a first set of n private caches at memory level two, with the first and second processors being exclusively operative with the first and second private caches, respectively, and the nth private cache being exclusively operative with the nth private cache, including means for transferring a page of information to one of said n private caches from main memory when at least one of the WRITE and SHARE flags are not in said given predetermined state, indicative of a page not being both writeable and shareable;
• a second shared cache at memory level one, which is operative with each of said n processors, including means for transferring lines of information from said first shared cache to said second shared cache;
• and
• a second set of n private caches at memory level one, with the first and second processors being exclusively operative with the first and second private caches, respectively, and the nth private cache being exclusively operative with the nth private cache, including means for transferring lines of information from the first set of n private caches to the second set of n private caches.

In a multiprocessor system, including a three level memory hierarchy, the combination comprising:

• at least first and second processors;
• a main memory at memory level three, in which sets of information, each set comprised of a plurality of subsets, are stored at addressable locations, with each set including a WRITE flag and a SHARE flag, with the state of the WRITE flag determining if each subset in a set is writeable or read only by a processor, and the state of the SHARE flag determining if each subset in the set is shareable or non-shareable by all processors, with each flag being established in a predetermined state;
• a first shared cache at memory level two, which is operative with each of said first and second processors, including means for transferring a set of information from main memory to said first shared cache when the WRITE and SHARE flags are each in a given predetermined state indicative of said set of information being both writeable and shareable, and a subset in said set being requested by one of said first and second processors;
• at least first and second private caches at memory level two, which are exclusively operative with said first and second processors, respectively, including means for transferring a set of information to one of said first and second private caches from main memory when at least one of the WRITE and SHARE flags are not in said given predetermined state, indicative of a set not being both writeable and shareable, and a subset in said set of information being requested by said first or second processor;
• a second shared cache at memory level one, which is operative with each of said first and second processors, including means for transferring subsets of information from said first shared cache to said second shared cache when requested by either of said first and second processors;
• and
• at least third and fourth private caches at memory level one, which are exclusively operative with said first and second processors, respectively, including means for transferring subsets of information from said first and second private caches, to said third and fourth private caches, respectively, when requested by said first or second processors, respectively.

In a multiprocessor system, including a three level memory hierarchy, the combination comprising:

• at least first and second processors;
• a main memory at memory level three, in which sets of information, each set comprised of a plurality of subsets, are stored at addressable locations, with each set including a WRITE flag and a SHARE flag, with the state of the WRITE flag determining if each subset in the set is writeable or read only by a processor, and the state of the SHARE flag determining if each subset in the set is shareable or non-shareable by all processors, with each flag being established in a predetermined state;
• at least first and second private caches at memory level two, which are operative with each of said first and second processors, including means for transferring a set of information to said first private cache when requested by said first processor and transferring a set of information to said second private cache when requested by said second processor from main memory for all combinations of states of the WRITE and SHARE flags;
• a shared cache at memory level one, which is operative with each of said first and second processors, including means for transferring a subset of information to said shared cache from either of said first and second private caches when the WRITE and SHARE flags, for the set in which the subset resides, are each in a given predetermined state indicative of said set of information being both writeable and shareable, when requested by either of said first and second processors;
• and
• at least third and fourth private caches at memory level one, which are exclusively operative with said first and second processors, respectively, including means for transferring a subset of information, to said third private cache from said first private cache when requested by said first processor, or to said fourth private cache from said second private cache when requested by said second processor when at least one of the WRITE and SHARE flags, for the set in which the subset resides, is not in said given predetermined state indicative of said set of information not being both writeable and shareable.