Multi-array operation support and related devices, systems and software

A method of operating a memory system, the memory system comprising a host device and a flash memory controller to manage flash memory comprising multiple planes, the method comprising:

• pre-establishing a first range of addresses that are to be used for multi-plane writes of data into the flash memory and a second range of addresses that are to be used for single plane writes of data into the flash memory;
• and
• during operation of the host device, causing the host device to issue memory access requests to the flash memory controller integrated circuit in dependence on whether an address associated with a given one of the memory access requests corresponds to the first range of addresses or to the second range of addresses, wherein the memory access requests are to cause the flash memory controller integrated circuit to access a variable number of the planes in dependence on the address associated with the given one of the memory access requests, such that a first address corresponding to a first memory access request causes the flash memory controller integrated circuit to exchange respective subsets of data associated with the first memory access request with respective ones of the planes, and such that a second address corresponding to a second memory access request causes the flash memory controller integrated circuit to exchange all of the data associated with the second memory access request with a single one of the planes only.

An apparatus comprising instructions stored on non-transitory, machine-readable media, the instructions to be executed by at least one hardware processor of a host device to direct memory access requests to a flash memory controller integrated circuit, the flash memory controller integrated circuit to manage flash memory comprising multiple planes, the instructions when executed to cause the at least one hardware based processor to:

• pre-establish a first range of addresses that are to be used for multi-plane writes of data into the flash memory and a second range of addresses that are to be used for single plane writes of data into the flash memory;
• and
• during operation of the host device, cause the host device to issue the memory access requests to the flash memory controller integrated circuit in dependence on whether an address associated with a given one of the memory access requests corresponds to the first range of addresses or to the second range of addresses, wherein the memory access requests are to cause the flash memory controller integrated circuit to access a variable number of the planes in dependence on the address associated with the given one of the memory access requests, such that a first address corresponding to a first memory access request causes the flash memory controller integrated circuit to exchange respective subsets of data associated with the first memory access request with respective ones of the planes, and such that a second address corresponding to a second memory access request causes the flash memory controller integrated circuit to exchange all of the data associated with the second memory access request with a single one of the planes only.