G06F 2207/4816
Pass transistors
G06F2207/4816 (Pass transistors) appears on 20 US grants and 3 published applications in this corpus.
Search patents in G06F- Granted patents
- 20
- Published applications
- 3
- Assignees
- 16
- Inventors
- 34
- Latest grant
- 4 Oct 2011
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1978 | 1 | 0 |
| 1979 | 0 | 0 |
| 1980 | 0 | 0 |
| 1981 | 0 | 0 |
| 1982 | 0 | 0 |
| 1983 | 0 | 0 |
| 1984 | 1 | 0 |
| 1985 | 0 | 0 |
| 1986 | 2 | 0 |
| 1987 | 2 | 0 |
| 1988 | 0 | 0 |
| 1989 | 0 | 0 |
| 1990 | 0 | 0 |
| 1991 | 3 | 0 |
| 1992 | 0 | 0 |
| 1993 | 1 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 3 | 0 |
| 1997 | 0 | 0 |
| 1998 | 1 | 0 |
| 1999 | 2 | 0 |
| 2000 | 2 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 1 |
| 2005 | 0 | 0 |
| 2006 | 0 | 0 |
| 2007 | 1 | 0 |
| 2008 | 0 | 1 |
| 2009 | 0 | 0 |
| 2010 | 0 | 0 |
| 2011 | 1 | 0 |
| 2012 | 0 | 0 |
| 2013 | 0 | 0 |
| 2014 | 0 | 0 |
| 2015 | 0 | 0 |
| 2016 | 0 | 0 |
| 2017 | 0 | 0 |
| 2018 | 0 | 0 |
| 2019 | 0 | 0 |
| 2020 | 0 | 0 |
| 2021 | 0 | 0 |
| 2022 | 0 | 0 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 0 | 1 |
By publication year. Applications have been published since 2001.
Recent patents
- CSA 5-3 compressor circuit and carry-save adder circuit using same4 Oct 2011US 8,032,819 B2Fujitsu Limited
- Arithmetic structures for programmable logic devices27 Feb 2007US 7,185,035 B1Altera Corporation
- Energy economized pass-transistor logic circuit and full adder using the same19 Sep 2000US 6,121,797 ASamsung Electronics Co., Ltd.
- Conditional sum adder using pass-transistor logic and integrated circuit having the same4 Jan 2000US 6,012,079 ASamsung Electronics Co., Ltd.
- Arithmetic processing2 Nov 1999US 5,978,827 ACanon Kabushiki Kaisha
- Full adder circuit and methods for high speed computing applications21 Aug 2025US 2025/0265039 A1Samsung Electronics Co., Ltd.
- CSA 5-3 compressor circuit and carry-save adder circuit using same28 Feb 2008US 2008/0052611 A1Fujitsu Limited
- Unified multiplier triple-expansion scheme and extra regular compact low-power implementations with borrow parallel counter circuits2 Sep 2004US 2004/0172439 A1The Research Foundation of State University of New York
Most cited
By later US patents
- Arithmetic processing107US 5,978,827 ACanon Kabushiki Kaisha · 1999
- Combinational logic structure using PASS transistors71US 4,566,064 AAmerican Microsystems, Inc. · 1986
- Transmission gate logic design method49US 5,200,907 A1993
- Transmission gate multiplexer (TGM) logic circuits and multiplier architectures48US 5,040,139 A1991
- Combinational logic structure using PASS transistors33US 4,622,648 AAmerican Microsystems, Inc. · 1986