US 6,012,079 A · Conditional sum adder using pass-transistor logic and integrated circuit having the same

Abstract

Disclosed is an integrated pass-transistor logic circuit which includes a conditional sum adder. This sum adder has seven sum generation blocks of module form and two carry generation blocks. With the sum adder, before carry propagation which is generated through multiplexer chain in respective sum generation blocks arrives at the final stage of the multiplexer chain, the final stage is driven by block carry signals BC.sub.i and /BC.sub.i provided from the respective carry generation blocks. The carry generation and the sum generation occur individually in the conditional sum adder. The sum generation blocks are constituted with pass-transistor logic and the carry generation blocks with Complementary Metal Oxide Semiconductor (CMOS) logic, the sum adder has a more faster operation speed and a more lower power dissipation, as compared with the prior art conditional sum adder having either the pass-transistor logic or the CMOS logic.

Claims44

Dependent claims

An N-bit conditional sum adder, wherein N is the number of adding bits, comprising:

K M-bit sum generators, wherein K is equal to .left brkt-top.N/M.right brkt-top.;
and
X L-bit carry generators, wherein X is equal to .left brkt-top.K/L.right brkt-top., wherein:
.left brkt-top..right brkt-top. represents the ceiling flnction, which returns the smallest integer greater than or equal to its operand;
each of the M-bit sum generators receives a first M-bit input signal, a complementary signal to the first M-bit input signal, a second M-bit input signal, a complementary signal to the second M-bit input signal, one carry signal corresponding to an L-bit carry signal or a complementary signal to the L-bit carry signal and a complementary signal to the carry signal, and generates an M-bit sum signal, an M-bit carry generation signal, and an M-bit carry propagation signal;
the first to the (X-1)-th carry generator of the X L-bit carry generators each receive an (L.times.M)-bit carry generation signal and an (L.times.M)-bit carry propagation signal from L corresponding M-bit sum generators of the K M-bit sum generators, and generate the L-bit carry signal and the complementary signal to the L-bit carry signal;
and
the X-th carry generator of the X L-bit carry generators receives the carry generation and carry propagation signals from the other M-bit sum generators of the K M-bit sum generators, and generates the carry signal and the complementary signal to the carry signal.

5 more elements

An N-bit conditional sum adder, wherein N is the number of adding bits, comprising:

K 16-bit sum generators, wherein K is equal to N/16;
and
X 4-bit carry generators, wherein X is equal to K/4, wherein:
each of the 16-bit sum generators receives a first 16-bit input signal, a complementary signal to the first 16-bit input signal, a second 16-bit input signal, a complementary signal to the second 16-bit input signal, one carry signal corresponding to a 4-bit carry signal or a complementary signal to the 4-bit carry signal, and a complementary signal to the carry signal, and generates a 16-bit sum signal, a 16-bit carry generation signal, and a 16-bit carry propagation signal;
the first to the (X-1)-th carry generator of the X 4-bit carry generators each receive a (4.times.16)-bit carry generation signal and a (4.times.16)-bit carry propagation signal from 4 corresponding 16-bit sum generators of the K 16-bit sum generators, and generate the 4-bit carry signal and the complementary signal to the 4-bit carry signal;
the X-th carry generator of the X 4-bit carry generators receives the carry generation and carry propagation signals from the other 16-bit sum generators of the 16-bit sum generators, and generates the carry signal and the complementary signal to the carry signal;
and
each of the 16-bit sum generators comprises:
means for receiving the first 16-bit input signal, the complementary signal to the first 16-bit input signal, the second 16-bit input signal, and the complementary signal to the second 16-bit input signal;
means for generating a first 16-bit conditional sum signal, a second 16-bit conditional sum signal, a 16-bit carry propagation signal, a complementary signal to the 16-bit carry propagation signal, a 16-bit carry generation signal and a complementary signal to the 16-bit carry generation signal;
means for receiving the first 16-bit conditional sum signal, the second 16-bit conditional sum signal, the 16-bit carry propagation signal, the complementary signal to the 16-bit propagation signal, the 16-bit carry generation signal, the complementary signal to the 16-bit carry generation signal, one carry signal corresponding to the 4-bit carry signal or the complementary signal to the 4-bit carry signal, and a complementary signal to the carry signal;
and
means for generating the 16-bit sum signal.

10 more elements

A conditional sum adder comprising:

first to seventh 16-bit sum generators;
and
first and second 4-bit carry generators, wherein:
each of the 16-bit sum generators receives a first 16-bit input signal, a complementary signal to the first 16-bit input signal, a second 16-bit input signal, a complementary signal to the second 16-bit input signal, one carry signal corresponding to a 4-bit carry signal or a complementary signal to the 4-bit carry signal, and a complementary signal to the carry signal, and generates a 16-bit sum signal;
the first 4-bit carry generator receives a 64-bit carry generation signal and a 64-bit carry propagation signal provided by the first to the fourth 16-bit sum generators, and generates the 4-bit carry signal and the complementary signal to the 4-bit carry signal;
and
the second 4-bit carry generator receives a 48-bit carry generation signal and a 48-bit carry propagation signal provided by the fifth to seventh 16-bit sum generators, and generates the carry signal and the complementary signal to the carry signal.

4 more elements

An N-bit conditional sum adder, wherein N is the number of adding bits, comprising:

K M-bit sum generators, each of which receives a first M-bit input signal, a complementary signal to the first M-bit input signal, a second M-bit input signal, a complementary signal to the second M-bit input signal, one carry signal corresponding to an L-bit carry signal or the complementary signal to the L-bit carry signal, and a complementary signal to the carry signal, and generates an M-bit sum signal, wherein K is equal to .left brkt-top.N/M.right brkt-top.;
and
X L-bit carry generators, each of which receives an (L.times.M)-bit carry generation signal and an (L.times.M)-bit carry propagation signal from L corresponding sum generators, and generates an L-bit carry signal and a complementary signal to the L-bit carry signal, wherein X is equal to .left brkt-top.K/L.right brkt-top., wherein:
.left brkt-top..right brkt-top. represents the ceiling function, which returns the smallest integer greater than or equal to its operand;
and
each of the M-bit sum generators comprises:
a (6.times.M)-bit pre-carry and pre-sum generation block for receiving the first M-bit input signal, the complementary signal to the first M-bit input signal, the second M-bit input signal, and the complementary signal to the second M-bit input signal, and generating a first M-bit conditional sum signal, a second M-bit conditional sum signal, an M-bit carry propagation signal, a complementary signal to the M-bit carry propagation signal, an M-bit carry generation signal and a complementary signal to the M-bit carry generation signal;
and
an M-bit carry lookahead addition block for receiving the first M-bit conditional sum signal, the second M-bit conditional sum signal, the M-bit carry generation signal, the complementary signal to the M-bit carry generation signal, the M-bit carry propagation signal, the complementary signal to the M-bit carry propagation signal, one carry signal corresponding to the L-bit carry signal or the complementary signal of the L-bit carry signal, and the complementary signal to the carry signal, and generating the M-bit sum signal.

6 more elements

A conditional sum adder comprising:

seven sum generators, each of which receives a first M-bit input signal, a complementary signal to the first M-bit input signal, a second M-bit input signal, a complementary signal to the second M-bit input signal, one bit of a 4-bit carry signal, and a complementary signal to the one bit of the 4-bit carry signal, and generates a M-bit sum signal;
and
two carry generators, the first of which receives a (4.times.M)-bit carry generation signal and a (4.times.M)-bit carry propagation signal from four corresponding sum generators, and generates a 4-bit carry signal and a complementary signal to the 4-bit carry signal, and the second of which receives a (3.times.M)-bit carry generation signal and a (3.times.M)-bit carry propagation signal from three corresponding sum generators, and generates a 3-bit carry signal and a complementary signal to the 3-bit carry signal,
wherein each of the two sum generators comprises:
a pre-carry and pre-sum generation block for receiving the first M-bit input signal, the complementary signal to the first M-bit input signal, the second M-bit input signal, and the complementary signal to the second M-bit input signal, and generating a first M-bit conditional sum signal, a second M-bit conditional sum signal, a M-bit carry propagation signal, a complementary signal to the M-bit carry propagation signal, a M-bit carry generation signal, and a complementary signal to the M-bit carry generation signal;
and
an M-bit carry lookahead addition block for receiving the first M-bit conditional sum signal, the second M-bit conditional signal, the M-bit carry propagation signal, the complementary signal to the M-bit carry propagation signal, the M-bit carry generation signal, the complementary signal to the M-bit carry generation signal, the one bit of the 4-bit carry signal, and the complementary signal to the one bit of the 4-bit carry signal, and generating the sum signal;
and
wherein each of the two carry generators comprises:
a group of four first carry lookahead addition sections, each of which receives a corresponding M-bit carry generation signal and a corresponding M-bit carry propagation signal and generates a 1-bit carry generation signal and a 1-bit carry propagation signal;
and
a second carry lookahead addition section for receiving the 1-bit carry generation signals and the 1-bit carry propagation signals from the group of four first carry lookahead addition sections, one bit of the 4-bit carry signal, and a complementary signal to the one bit of the 4-bit carry signal, and generating the 4-bit carry signal and the complementary signal to the 4-bit carry signal.

9 more elements

An N-bit conditional sum adder wherein N is the number of adding bits, comprising:

K M-bit sum generators, each of which receives a first M-bit input signal, a complementary signal to the first M-bit input signal, a second M-bit input signal, a complementary signal to the second M-bit input signal, one carry signal corresponding to an L-bit carry signal or the complementary signal to the L-bit carry signal, and a complementary signal to the carry signal, and generates an M-bit sum signal, wherein K is equal to .left brkt-top.N/M.right brkt-top. and .left brkt-top..right brkt-top. represents the ceiling function, which returns the smallest integer greater than or equal to its operand;
and
X L-bit carry generators, each of which receives an (L.times.M)-bit carry generation signal and an (L.times.M)-bit carry propagation signal from L corresponding sum generators and generates an L-bit carry signal and a complementary signal to the L-bit carry signal, wherein X is equal to .left brkt-top.K/L.right brkt-top.,
wherein each of the M-bit sum generators comprises:
a pre-carry and pre-sum generation block for receiving the first M-bit input signal, a complementary signal to the first M-bit input signal, a second M-bit input signal, and a complementary signal to the second M-bit input signal and generating a first M-bit conditional sum signal, a second M-bit conditional sum signal, an M-bit carry propagation signal, a complementary signal to the M-bit carry propagation signal, an M-bit carry generation signal, and a complementary signal to the M-bit carry generation signal;
and
an M-bit carry lookahead addition block for receiving the first M-bit conditional sum signal, the second M-bit conditional sum signal, the M-bit carry generation signal, the complementary signal to the M-bit carry generation signal, the M-bit carry propagation signal, the complementary signal to the M-bit carry propagation signal, one carry signal corresponding to the L-bit carry signal or the complementary signal to the L-bit carry signal, and the complementary signal to the carry signal and generating the M-bit sum signal;
and
wherein each of the X L-bit carry generators comprises:
a group of first carry lookahead addition sections, each of which receives a corresponding M-bit carry generation signal and a corresponding M-bit carry propagation signal and generates a 1-bit carry generation signal and a 1-bit carry propagation signal;
and
a second carry lookahead addition section for receiving the carry generation signals and the carry propagation signals from the group of first carry lookahead addition sections and generating the L-bit carry signals and the complementary signals to the L-bit carry signals.

9 more elements

An integrated pass-transistor logic circuit comprising:

an encoding means for receiving a first 54-bit data signal and a second 54-bit data signal and generating a first to a fifty-fourth 54-bit vertical data signals, wherein the encoding means generates the second 54-bit data signal as a corresponding vertical data signal when a bit value of the first 54-bit data signal is at logical "1" state, and generates a vertical data signal of logical "0" state when a bit value of the first 54-bit data signal is at logical "0" state;
a compressing means for receiving the first to fifty-fourth vertical data signals and compressing each of the vertical data signals to a 2-bit signal to generate a 54-bit sum signal and a 54-bit carry signal;
and
an adding means for adding the 54-bit sum signal and the 54-bit carry signal from the compressing means, wherein the adding means comprises:
a first to a seventh 16-bit sum generators, each of which receives a first 16-bit input signal, a complementary signal to the first 16-bit input signal, a second 16-bit input signal, a complementary signal to the second 16-bit input signal, a carry signal corresponding to a 4-bit carry signal or to a complementary signal to the 4-bit carry signal, and a complementary signal to the carry signal and generates a 16-bit sum signal;
a first carry generator for receiving a 64-bit carry generation signal and a 64-bit carry propagation signal from four corresponding sum generators and generating the 4-bit carry signal and the complementary signal to the 4-bit carry signal;
and
a second carry generator for receiving the other carry generation and propagation signals and generating the carry signal and the complementary signal to the carry signal.

5 more elements

Dependencies are inferred from the claim text.

Conditional sum adder using pass-transistor logic and integrated circuit having the same

Life of this patent

Conditional sum adder using pass-transistor logic and integrated circuit having the same

Life of this patent

Abstract

Claims44