Unified multiplier triple-expansion scheme and extra regular compact low-power implementations with borrow parallel counter circuits

A multiplier circuit including borrow parallel multiplier circuits and virtual multiplier circuits using borrow parallel counters providing low-power, high-speed, and small-area features, said multiplier comprising:

• regular and unified layouts for small multipliers of n×n, where 3≦n≦9 including a single array of almost identical borrow counters;
• reduced line connections including partial product bits generations and their connections to the bit reduction networks;
• and
• a substantially same delay for almost all output bits, wherein transistor sizing and delay equalization is minimized.

A multiplier circuit utilizing 4-b 1-hot encoded signals and borrow bits, the circuit comprising:

• at least two input numbers, each of said input numbers being trisected into three segments;
• a plurality of Carry Select Adders (CSAs);
• a plurality of multipliers interconnected to the CSAs, said multipliers being arranged to minimize the interconnection to the CSAs;
• and
• a plurality of output bits.

A small borrow parallel multiplier circuit for processing a plurality of bit inputs, the multiplier comprising:

• an array including a plurality of identical counters with a simple layout arranged in a plurality of columns, wherein “borrow-effect” naturally re-arranges bits being processed so that an actual number of bits processed in each column are balanced;
• minimal line connections within each line, wherein a single counter is used in each column;
• and
• a plurality of output bits having similar delay, wherein said multiplier requiring little cost in transistor sizing and delay equalization.