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US 8,032,819 B2Granted
CSA 5-3 compressor circuit and carry-save adder circuit using same
AssigneeFujitsu Limited
InventorKazuhiro Abe
Life of this patent
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Abstract
At least two Exclusive-OR (EOR) circuits for carry-out which output carry-out bits and the complementary signals thereof are provided in the 5-3 compressor circuits constituted by an Exclusive-OR (EOR) circuit group, and dual lanes are employed at least for carry-out. As a result, the number of inverters required can be reduced, increases in delay time can be suppressed, and fast addition operation can be achieved.
Claims12
A 5-3 compressor circuit for Carry-Save Adder (CSA) which receives four input signals and a lower-digit carry-out input, and computes addition bits, carry bits, and carry-out bits, comprising:
- four first-stage Exclusive-OR (EOR) circuits, which receive said four input signals and complementary signals of said four input signals, perform Exclusive-OR (EOR) computation of two input signals, and output two Exclusive-OR (EOR) outputs and complementary signals of said two Exclusive-OR (EOR) outputs;
- two second-stage Exclusive-OR (EOR) circuits, which receive the outputs of said four first-stage Exclusive-OR (EOR) circuits, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs, and output one Exclusive-OR (EOR) output and the complementary signal of said Exclusive-OR (EOR) output;
- a third-stage Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits and said carry-out bits, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs and said carry-out bits, and outputs addition bits;
- a carry output Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits, said carry-out bits, and one of said four input signals, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs, said carry-out bits, and said one input signal, and outputs carry bits;
- and
- two carry-out Exclusive-OR (EOR) circuits, which receive the outputs of said two first-stage Exclusive-OR (EOR) circuits and two complementary signals of said input signals, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs and said two complementary signals, and output said carry-out bits and the complementary signals thereof.
3 more elements
A carry-save adder circuit comprising:
- a plurality of 5-3 compressor circuits for Carry-Save Adder (CSA), which receive four input signals and a lower-digit carry-out input, and compute addition bits, carry bits, and carry-out bits, and connected by said carry-out inputs,
- wherein each of said 5-3 compressor circuits for Carry-Save Adder (CSA) comprises:
- four first-stage Exclusive-OR (EOR) circuits, which receive four input signals and complementary signals thereof, perform Exclusive-OR (EOR) computation of every two input signals, and output two Exclusive-OR (EOR) outputs and complementary signals thereof;
- two second-stage Exclusive-OR (EOR) circuits, which receive the outputs of said four first-stage Exclusive-OR (EOR) circuits, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs, and output one Exclusive-OR (EOR) output and the complementary signal thereof;
- a third-stage Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits and said carry-out bits, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs and said carry-out bits, and outputs addition bits;
- a carry output Exclusive-OR (EOR) circuit, which receives the outputs of said two second-stage Exclusive-OR (EOR) circuits, said carry-out bits, and one of said four input signals, performs Exclusive-OR (EOR) computation of said Exclusive-OR (EOR) outputs, said carry-out bits, and said one input signal, and outputs carry bits;
- and
- two carry-out Exclusive-OR (EOR) circuits, which receive the outputs of said two first-stage Exclusive-OR (EOR) circuits and two complementary signals of said input signals, perform Exclusive-OR (EOR) computation of said two Exclusive-OR (EOR) outputs and said two complementary signals, and output said carry-out bits and the complementary signals thereof.
5 more elements
Dependencies are inferred from the claim text.