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US 7,185,035 B1Granted
Arithmetic structures for programmable logic devices
AssigneeAltera Corporation
InventorsDavid Lewis, Bruce Pedersen, Sinan Kaptanoglu
Life of this patent
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Abstract
According to some embodiments, arithmetic structures in logic elements result from combining inverters and pass gates (or other multiplexing hardware) with LUT hardware. According to other embodiments, arithmetic structures in logic elements result from combining dedicated adder hardware (e.g., including XOR units) and fracturable LUT hardware. According to other embodiments, arithmetic structures in logic elements result from providing complementary input connections between multiplexers and LUT hardware. In this way, the present invention enables the incorporation of arithmetic structures with LUT structures in a number of ways.
Claims56
A logic element, comprising:
- a plurality of LUTs (look-up tables);
- a plurality of inverters connected to the LUTs;
- a plurality of pass gates connected to the LUTs and the inverters;
- an output multiplexer connected to the pass gates;
- a carry-chain input;
- a carry-chain unit connected to the LUTs and the carry-chain input;
- and
- a plurality of controls connected to the LUTs, the pass gates, the output multiplexer, and the carry-chain unit, wherein
- in a logic mode the output multiplexer provides a logic function of the controls, and
- in an arithmetic mode the output multiplexer provides an arithmetic sum of two logic functions of the controls where the carry-chain unit provides a corresponding carry-chain output.
7 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having a plurality of fractured outputs, including a first fractured output and a second fractured output;
- a carry-chain input;
- and
- a carry-out select multiplexer connected to the carry-chain input, the first fractured output and the second fractured output;
- an XOR unit connected to the carry-chain input and the second fractured output, wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the XOR unit provides an arithmetic sum of the additive control and a second logic function of the controls where the carry-out select multiplexer provides a corresponding carry-chain output.
6 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the data multiplexers and the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having at least one fractured output, including a first fractured output;
- a carry-chain input;
- a carry-out select multiplexer connected to the carry-chain input, the first fractured output and the additive control;
- and
- an XOR unit connected to the carry-chain input and the first fractured output, wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the XOR unit provides an arithmetic sum of the additive control and a second logic function of the controls where the carry-out select multiplexer provides a corresponding carry-chain output.
6 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the data multiplexers and the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having at least one fractured output, including a first fractured output;
- a carry-chain input;
- a carry-out select multiplexer connected to the carry-chain input, the first fractured output and the output multiplexer;
- and
- an XOR unit connected to the carry-chain input and the output mulitplexer, wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the XOR unit provides an arithmetic sum of the additive control and a second logic function of the controls where the carry-out select multiplexer provides a corresponding carry-chain output.
6 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having a plurality of fractured outputs, including a first fractured output and a second fractured output;
- a carry-chain input;
- a carry-out select multiplexer connected to the carry-chain input and the additive control;
- an internal XOR unit connected to the second fractured output, the additive control, and the carry-out select multiplexer;
- and
- an output XOR unit connected to the carry-chain input and the internal XOR unit, wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the second fractured output provides a second logic function of the controls, the first fractured output provides a third logic function of the controls, and the output XOR unit provides an arithmetic sum of the additive control and the second logic function of the controls where the carry-out select multiplexer provides a corresponding carry-chain output.
7 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having a plurality of fractured outputs, including a first fractured output and a second fractured output;
- a carry-chain input;
- a carry-out select multiplexer connected to the carry-chain input and the second fractured output;
- an internal XOR unit connected to the second fractured output, the additive control, and the carry-out select multiplexer;
- and
- an output XOR unit connected to the carry-chain input and the internal XOR unit,
- wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the second fractured output provides a second logic function of the controls, the first fractured output provides a third logic function of the controls, and the output XOR unit provides an arithmetic sum of the additive control and the second logic function of the controls where the carry-out select multiplexer provides a corresponding carry-chain output.
8 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the LUTs, the data multiplexers including an output multiplexer;
- a plurality of controls connected to the data multiplexers and the LUTs, so that the LUTs, the data multiplexers and the controls define a fracturable LUT having a plurality of fractured outputs, including a first fractured output, a second fractured output, and a third fractured output;
- a carry-chain input;
- and
- an adder unit connected to the first fractured output and the second fractured output and the carry-chain input, wherein
- in a logic mode the output multiplexer provides a first logic function of the controls, and
- in an arithmetic mode the first fractured output provides a second logic function of the controls, the third fractured output provides a third logic function of the controls, and the adder unit provides an arithmetic sum of the second logic function of the controls and the third logic function of the controls where the adder unit provides a corresponding carry-chain output.
5 more elements
A logic element, comprising:
- a plurality of LUTs;
- a plurality of data multiplexers connected to the LUTs, the data multiplexers including an output multiplexer, a first complementary multiplexer, and a second complementary multiplexer, so that the first complementary multiplexer and the second complementary multiplexer have complementary connections to the LUTs;
- a plurality of controls connected to the data multiplexers and the LUTs, the controls including an additive control;
- a carry-chain input connected to the output multiplexer;
- and
- a carry-out select multiplexer connected to the carry-chain input, the additive control and the data multiplexers, wherein
- in a logic mode the first complementary multiplexer provides a logic function of the controls, and
- in an arithmetic mode the output multiplexer provides an arithmetic modification of the logic function of the controls where the additive control is replaced by an arithmetic sum and the carry-out select multiplexer provides a corresponding carry-chain output.
5 more elements
Dependencies are inferred from the claim text.