G06F 2117/02
Fault tolerance
Official title: Fault tolerance, e.g. for transient fault suppression
G06F2117/02 (Fault tolerance) appears on 107 US grants and 110 published applications in this corpus.
Search patents in G06F- Granted patents
- 107
- Published applications
- 110
- Assignees
- 74
- Inventors
- 308
- Latest grant
- 17 Mar 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1989 | 1 | 0 |
| 1990 | 0 | 0 |
| 1991 | 0 | 0 |
| 1992 | 0 | 0 |
| 1993 | 0 | 0 |
| 1994 | 0 | 0 |
| 1995 | 0 | 0 |
| 1996 | 0 | 0 |
| 1997 | 0 | 0 |
| 1998 | 0 | 0 |
| 1999 | 0 | 0 |
| 2000 | 0 | 0 |
| 2001 | 0 | 0 |
| 2002 | 0 | 0 |
| 2003 | 0 | 0 |
| 2004 | 0 | 1 |
| 2005 | 1 | 0 |
| 2006 | 0 | 0 |
| 2007 | 1 | 1 |
| 2008 | 0 | 3 |
| 2009 | 0 | 1 |
| 2010 | 2 | 2 |
| 2011 | 4 | 4 |
| 2012 | 2 | 2 |
| 2013 | 5 | 10 |
| 2014 | 9 | 4 |
| 2015 | 5 | 7 |
| 2016 | 7 | 5 |
| 2017 | 8 | 6 |
| 2018 | 4 | 2 |
| 2019 | 6 | 12 |
| 2020 | 7 | 9 |
| 2021 | 11 | 8 |
| 2022 | 11 | 13 |
| 2023 | 8 | 8 |
| 2024 | 6 | 6 |
| 2025 | 6 | 5 |
| 2026 | 3 | 1 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
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- Method and system for manufacturing integrated circuit device6 Jan 2026US 12,520,579 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Method and system for latch-up prevention9 Sep 2025US 12,412,019 B2Taiwan Semiconductor Manufacturing Company.Ltd
- Techniques for generating a configuration for electrically isolating fault domains in a data center5 Aug 2025US 12,380,258 B2Oracle International Corporation
- Integrated circuit device2 Apr 2026US 2026/0096207 A1Taiwan Semiconductor Manufacturing Company.Ltd
- System and method for source synchronous implementation13 Nov 2025US 2025/0348106 A1Microsoft Technology Licensing, LLC
- Integrated circuit design with protection based on protected declaration and annotation30 Oct 2025US 2025/0335675 A1SiFive, Inc.
- System and method for using interface protection parameters9 Oct 2025US 2025/0315584 A1Arteris, Inc.
- Optimizing the error checking logic in a processor5 Jun 2025US 2025/0181809 A1International Business Machines Corporation
Most cited
By later US patents
- System integrated fault-tree analysis methods (SIFTAN)29US 4,870,575 AITT Corporation · 1989
- Visualization of tradeoffs between circuit designs23US 9,087,164 B2National Semiconductor Corporation · 2015
- Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA22US 7,249,010 B1Xilinx, Inc. · 2007
- Method for performing failure mode and effects analysis of an integrated circuit and computer program product therefor17US 7,937,679 B2Yogitech S.p.A. · 2011
- Reliability simulation method for a PCB assembly11US 7,707,525 B2Expert Dynamics, Ltd. · 2010