Methods of estimating susceptibility to single event upsets for a design implemented in an FPGA

An article of manufacture, comprising:

• a computer-readable storage medium comprising computer-executable code for estimating the susceptibility to single event upsets (SEUs) of a design implemented in a field programmable gate array (FPGA), the medium comprising:
• code for determining resources of the FPGA used in the design;
• code for selecting one of the resources used in the design;
• code for determining a number of configuration bits associated with the selected resource;
• code for setting a number of resource bits to the number of configuration bits associated with the selected resource;
• code for setting the number of care bits to a previous number of care bits plus the number of resource bits;
• code for executing, for each resource used in the design, the code for selecting one of the resources used in the design, the code for determining the number of configuration bits, the code for setting the number of resource bits, and the code for setting the number of care bits;
• and
• code for setting an SEU Probability Impact (SEUPI) value to the number of care bits divided by a total number of configuration memory cells in the FPGA.

A computer system for estimating the susceptibility to single event upsets (SEUs) of a design implemented in a field programmable gate array (FPGA), the system comprising:

• a resource determining module for determining resources of the FPGA used in the design;
• a resource selecting module for selecting one of the resources used in the design;
• a configuration bit determining module for determining a number of configuration bits associated with the selected resource;
• a resource bit setting module for setting a number of resource bits to the number of configuration bits associated with the selected resource;
• a care bit setting module for setting the number of care bits to a previous number of care bits plus the number of resource bits;
• a code executing module for executing, for each resource used in the design, the resource selecting module, the configuration bit determining module, the resource bit setting module, and the care bit setting module;
• an SEU Probability Impact (SEUPI) value setting module for setting the SEUPI value to the number of care bits divided by a total number of configuration memory cells in the FPGA;
• and
• an output module for outputting the SEUPI value as an estimated SEU susceptibility for the design implemented in the FPGA,
• wherein the resource determining module, the resource selecting module, the configuration bit determining module, the resource bit setting module, the care bit setting module, the code executing module, the SEUPI value setting module, and the output module comprise modules stored on the computer system.

An article of manufacture, comprising:

• a computer-readable storage medium comprising computer-executable code for estimating the susceptibility to single event upsets (SEUs) of a design implemented in a field programmable gate array (FPGA), the medium comprising:
• a device resource and configuration bits model identifying a number of configuration bits associated with each resource in the FPGA;
• a design file comprising the design implemented in the FPGA;
• a resource identification tool for determining resources of the FPGA used in the design;
• a resource usage list comprising a list of resources from the FPGA identified by the resource identification tool as being used in the design;
• and
• an SEU Probability Impact (SEUPI) calculator for calculating a SEUPI value for the design in the FPGA.