Rollback for communication link error recovery in emulation

A reconfigurable hardware modeling device comprising:

• a plurality of reconfigurable hardware modeling circuits, each of the plurality of reconfigurable hardware modeling circuits comprising:
• a plurality of communication ports,
• error monitoring circuitry configured to monitor, while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, whether data received from the plurality of communication ports contain an error or not, and send out an error signal indicating the monitoring result, wherein the monitoring operation performed by the error monitoring circuitry comprises:
• determining, within one design clock cycle, whether data received from the plurality of communication ports at a rising edge, a falling edge, or both of the rising and falling edges of a design clock cycle immediately preceding the one design clock cycle contain an error or not, and
• generating the error signal within the one design clock cycle, and
• rollback circuitry, the rollback circuitry comprising storage elements for state elements in the each of the plurality of reconfigurable hardware modeling circuits configured to capture and store values currently stored in the state elements before the state elements perform state updating
• wherein the rollback circuitry is configured to,
• if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enable the each of the plurality of reconfigurable hardware modeling circuits to repeat the operation from a state before the error is received, wherein the enabling operation performed by the rollback circuitry includes transferring the value in the storage elements back to the state elements, wherein the repeating operation rolls the operation for verifying the circuit design back to the rising edge of the design clock cycle immediately preceding the one design clock cycle, and
• if data received by the plurality of reconfigurable hardware modeling circuits contain no error, allow the each of the plurality of reconfigurable hardware modeling circuits to continue the operation.

A method comprising:

• monitoring, by error monitoring circuitry in each of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device, whether data received from a plurality of communication ports in the each of the plurality of reconfigurable hardware modeling circuits contain an error or not while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, wherein the monitoring operation performed by the error monitoring circuitry comprises:
• determining, within one design clock cycle, whether data received from the plurality of communication ports at a rising edge, a falling edge, or both of the rising and falling edges of a design clock cycle immediately preceding the one design clock cycle contain an error or not, and
• generating the error signal within the one design clock cycle;
• sending out, by the error monitoring circuitry, an error signal indicating the monitoring result;
• if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enabling the each of the plurality of reconfigurable hardware modeling circuits by rollback circuitry in the each of the plurality of reconfigurable hardware modeling circuits to repeat the operation from a state before the error is received, including suppressing state update of a state element, wherein the repeating operation rolls the operation for verifying the circuit design back to the rising edge of the design clock cycle immediately preceding the one design clock cycle;
• and
• if data received by the plurality of reconfigurable hardware modeling circuits contain no error, continuing the operation by the reconfigurable hardware modeling device.

A method comprising:

• monitoring, by error monitoring circuitry in each of a plurality of reconfigurable hardware modeling circuits in a reconfigurable hardware modeling device, whether data received from a plurality of communication ports in the each of the plurality of reconfigurable hardware modeling circuits contain an error or not while the reconfigurable hardware modeling device is performing an operation for verifying a circuit design, wherein the monitoring operation performed by the error monitoring circuitry comprises:
• determining, within one design clock cycle, whether data received from the plurality of communication ports at a rising edge, a falling edge, or both of the rising and falling edges of a design clock cycle immediately preceding the one design clock cycle contain an error or not, and
• generating the error signal within the one design clock cycle;
• sending out, by the error monitoring circuitry, an error signal indicating the monitoring result;
• if data received by any of the plurality of reconfigurable hardware modeling circuits contain an error, enabling the each of the plurality of reconfigurable hardware modeling circuits by rollback circuitry in the each of the plurality of reconfigurable hardware modeling circuits to repeat the operation from a state before the error is received, wherein the rollback circuit comprises storage elements for state elements in the each of the plurality of reconfigurable hardware modeling circuits configured to capture and store values currently stored in the state elements before the state elements perform state updating, and wherein the enabling includes transferring the value in the storage elements back to the state elements, wherein the repeating operation rolls the operation for verifying the circuit design back to the rising edge of the design clock cycle immediately preceding the one design clock cycle;
• and
• if data received by the plurality of reconfigurable hardware modeling circuits contain no error, continuing the operation by the reconfigurable hardware modeling device.