Method and system for latch-up prevention
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPo-Chia Lai, Kuo-Ji Chen, Wen-Hao Chen, Wun-Jie Lin, Yu-Ti Su, Rabiul Islam, Shu-Yi Ying, Stefan Rusu, Kuan-Te Li, David Barry Scott
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Abstract
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
Claims20
A method, comprising:
- providing a cell library defining a plurality of functional cells configured to perform a predefined function and a plurality of tap cells;
- receiving an integrated circuit design;
- selecting a plurality of the functional cells from the cell library based on the integrated circuit design;
- arranging the plurality of the functional cells into a floor plan, wherein the floor plan includes a plurality of rows;
- arranging a plurality of the tap cells into predetermined locations of the floor plan;
- modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan;
- and
- determining potential latchup locations in the floor plan based on the voltage droop of the floor plan.
A method, comprising:
- selecting a plurality of functional cells, configured to perform predefined functions, from a cell library based on an integrated circuit design;
- arranging the plurality of functional cells into a floor plan;
- arranging a plurality of tap cells from the cell library into locations of the floor plan;
- modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan;
- and
- determining potential latchup locations in the floor plan based on the voltage droop of the floor plan.
A method, comprising:
- selecting a plurality of functional cells, configured to perform predefined functions, from a cell library based on an integrated circuit design;
- arranging the plurality of functional cells into a floor plan;
- arranging a plurality of tap cells from the cell library into locations of the floor plan;
- modeling AC and DC current of the functional cells of the floor plan to determine voltage droop of the floor plan;
- and
- determining potential latchup locations in the floor plan based on the voltage droop of the floor plan and determining whether the voltage droop exceeds a predetermined value.
Dependencies are inferred from the claim text.