G06F 15/17393
Having multistage networks
Official title: {having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining}
G06F15/17393 (Having multistage networks) appears on 107 US grants and 135 published applications in this corpus.
Search patents in G06F- Granted patents
- 107
- Published applications
- 135
- Assignees
- 51
- Inventors
- 198
- Latest grant
- 24 Feb 2026
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 1983 | 1 | 0 |
| 1984 | 0 | 0 |
| 1985 | 3 | 0 |
| 1986 | 4 | 0 |
| 1987 | 3 | 0 |
| 1988 | 2 | 0 |
| 1989 | 1 | 0 |
| 1990 | 3 | 0 |
| 1991 | 1 | 0 |
| 1992 | 2 | 0 |
| 1993 | 6 | 0 |
| 1994 | 7 | 0 |
| 1995 | 11 | 0 |
| 1996 | 6 | 0 |
| 1997 | 8 | 0 |
| 1998 | 9 | 0 |
| 1999 | 2 | 0 |
| 2000 | 2 | 0 |
| 2001 | 3 | 2 |
| 2002 | 1 | 5 |
| 2003 | 0 | 0 |
| 2004 | 0 | 0 |
| 2005 | 2 | 2 |
| 2006 | 1 | 1 |
| 2007 | 2 | 1 |
| 2008 | 1 | 0 |
| 2009 | 2 | 2 |
| 2010 | 0 | 1 |
| 2011 | 2 | 9 |
| 2012 | 1 | 0 |
| 2013 | 6 | 2 |
| 2014 | 0 | 4 |
| 2015 | 2 | 2 |
| 2016 | 5 | 1 |
| 2017 | 0 | 1 |
| 2018 | 1 | 2 |
| 2019 | 0 | 0 |
| 2020 | 2 | 1 |
| 2021 | 0 | 1 |
| 2022 | 3 | 2 |
| 2023 | 0 | 1 |
| 2024 | 1 | 2 |
| 2025 | 0 | 0 |
| 2026 | 1 | 93 |
By publication year. Applications have been published since 2001. 2026 runs to 8 Oct.
Recent patents
- Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process24 Feb 2026US 12,561,576 B2Deep Vision Inc.
- Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process2 Jul 2024US 12,026,628 B2Deep Vision Inc.
- Processor system and method for increasing data-transfer bandwidth during execution of a scheduled parallel process13 Dec 2022US 11,526,767 B2Deep Vision Inc.
- Emulating broadcast in a network on chip9 Aug 2022US 11,411,759 B2Siemens Industry Software Inc.
- Methods and apparatus for sharing nodes in a network with connections based on 1 to k+1 adjacency used in an execution array memory array (XarMa) processor15 Feb 2022US 11,249,939 B2
- Simultaneous Silicon Spring and Chip Singulation DRIE13 Aug 2026US 2026/0239987 A1
- High Current Column Grid Array Pillars13 Aug 2026US 2026/0240010 A1
- Targeted Jet-Cooling System for Zetta-Scale Computing Assemblies16 Jul 2026US 2026/0202891 A1
- Local-Bias Adaptive Drive for Timing Stabilization in Pipelined Mixed-Precision Processing Elements16 Jul 2026US 2026/0203017 A1
- Pipelined Fused Multiply-Add Processing Element for FP4 Weight and FP8 Activation Arithmetic with FP8 Accumulation16 Jul 2026US 2026/0203018 A1
Most cited
By later US patents
- Construction of hierarchical networks through extension167US 5,519,694 AMassachusetts Institute of Technology · 1996
- Multiprocessing packet switching connection system having provision for error correction and recovery142US 5,166,674 AInternational Business Machines Corporation · 1992
- Variable cyclic redundancy coding method and apparatus for use in a multistage network124US 5,734,826 AInternational Business Machines Corporation · 1998
- Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays119US 5,280,474 AMasPar Computer Corporation · 1994
- Switch network extension of bus architecture117US 5,617,547 AInternational Business Machines Corporation · 1997