Methods and apparatus for sharing nodes in a network with connections based on 1 to k+1 adjacency used in an execution array memory array (XarMa) processor
OwnerGerald George Pechanekinventor
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OwnerGerald George Pechanekinventor
Estimating the term…
An Execution Array Memory Array (XarMa©) processor is described for signal processing and internet of things (IoT) applications, (pronounced sharma, that means happiness in Sanskrit). The XarMa© processor uses a 1 to K+1 adjacency network in an array of execution units. The 1 to K+1 adjacency refers to connections separately made in rows and in columns of execution unit and local file nodes, where the number of Rows≥K>1 and of Columns≥K>1 and K is an odd integer. Instead of a large central multi-ported register file, a distributed set of storage files local to each execution unit is used. The instruction set architecture uses instructions that specify forwarding of execution results to execution units associated with destination instructions. This execution array is scalable to support cost effective and low power high-performance application specific processing focused on target product requirements.
A method of executing a sequence of instructions in an execution unit (E×U) node in an array of E×Units, the method comprising:
A network organized according to a 1 by Column (1×C) matrix, the network comprising:
A system apparatus comprising:
Dependencies are inferred from the claim text.