Scalable processor to processor and processor-to-I/O interconnection network and method for parallel processing arrays

A global router network for a massively parallel array of processing elements, the routing network comprising a plurality of data-routing stages, wherein each of said data-routing stages comprises:

• a route requesting input wire (RRW-x) for receiving a route-requesting header signal;
• a pipeline latch (612) having a data input terminal (D) and a data output terminal (Q);
• a first tristate buffer (611) for selectively coupling the route request input wire (RRW-x) to the data input terminal of the pipeline latch (612);
• a switching matrix (615) having a router header-in line (621x), horizontal data input lines (650x), vertical output lines (654Y) and switching cells (620) for selectively coupling any one of said horizontal input lines (650x) to one of the vertical output lines (654Y);
• a second tristate buffer (652) for selectively coupling the output terminal (Q) of the pipeline latch (612) to said horizontal input line (650x) of the switching matrix (615) during a forward messagingmode;
• a third tristate buffer (657) for selectively coupling said horizontal data line (650x) to the data input terminal (D) of the pipeline latch (612) during a reverse messaging mode;
• and
• a fourth tristate buffer (658) for selectively coupling the output terminal (Q) of the pipeline latch (612) to the route requesting wire (RRW-x) during the reverse messaging mode.

A method for routing data in a global router system between any one processor element (PE) of an array of processor elements (PEs) and any other PE of the array, comprising the steps of:

• providing an interconnection network for establishing data routing paths between a set of source PEs and a set of target PEs;
• furnishing said PEs with respectively parity identities having precomputed values based on the array addresses of the respective PEs;
• generating route requesting signals to be propagated at least in part through said interconnection network from the set of source PEs to the set of target Pes for establishing data carrying routes through said interconnection network in accordance with address information in said route requesting signals, each of said route requesting signals including a protocol bit for indicating to said interconnection network the presence of a route requesting signal;
• `generating parity bits respectively associated with said route requesting signals for propagating through said interconnection network to indicate respectively an odd or even parity of the addresses in said route requesting signals;
• and
• comparing in each PE of the set of target PEs receiving a parity bit the parity identity thereof with the received parity bit to indicate an error condition in the event the parity identity of said each PE and the parity bit received by said each PE are unequal.

In a parallel processor having an array of processor elements, an interconnection network for indirectly routing data from one set of the processor elements to another set of the processor elements comprising:

• a first bidirectional latch having a set of first ports and a set of second ports;
• first bidirectional routing path segments respectively connected to the first ports of the first latch, the first routing path segments including a first switch stage responsive to header data from the processor elements for configuring the first routing path segments;
• second bidirectional routing path segments respectively connected to the second ports of the first latch, the second routing path segments including a second switch stage responsive to header data from the first switch stage for configuring the second routing path segments;
• a second bidirectional latch having a set of first ports and a set of second ports, the first ports thereof being connected to the processor elements and the second ports thereof being respectively connected to the first routing path segments;
• a third bidirectional latch having a set of first ports and a set of second ports, the first ports thereof being respectively connected to the second routing path segments, and the second ports thereof being connected to the processor elements;
• third and fourth bidirectional routing path segments, wherein:
• the first ports of the second bidirectional latch are respectively connected to the processor elements by the third bidirectional routing path segments;
• and
• the second ports of the third bidirectional latch are respectively connected to the processor elements by the fourth bidirectional routing path segments;
• and
• means for operating the first, second and third latches and the processor elements to transfer data between one set of the processor elements and another set of the processor elements in either direction along routing paths comprising the configured first, second, third and fourth routing path segments.