Multiprocessing packet switching connection system having provision for error correction and recovery

A cluster connected multiprocessing system, comprising:

• a first plurality of processors, wherein each of said processors in said first plurality comprises a local memory;
• a second plurality of processors, wherein each of said processors in said second plurality comprises a local memory;
• first cluster controller means connected to receive first data from said first plurality of processors, for assembling said first data into a first plurality of packets comprising a source field, a destination field and a command field, and for outputting said first plurality of packets;
• second cluster controller means connected to receive second data from said second plurality of processors, for assembling said second data into a second plurality of packets comprising a source field, a destination field and a command field, and for outputting said second plurality of packets;
• and
• switching network means connected to receive said first and second plurality of packets from said first and second cluster controller means, for decoding said destination field and for determining which one of said cluster controller means is connected to an addressed processor corresponding to said destination field and for routing each of said packets in said first and second plurality to a corresponding one of said cluster controller means identified by said destination field.

A cluster controller for use in a multiprocessor system comprising a plurality of processing element clusters coupled by way of a switching network, said cluster controller comprising:

• switching means, connected to receive packets from said switching network, for distributing said packets from said switching network in accordance with a destination address contained in said packets;
• queue means, coupled to a plurality of said processing elements, for buffering packet flow to said plurality of processing elements, said queue means comprising a plurality of packet queues associated with each of said processing elements,
• assembly buffer means, coupled to said plurality of said processing elements, for assembling data from said processing elements into packets, said assembly buffer means comprising one assembly buffer for each of said processing elements;
• and
• selector means, coupled to said assembly buffer means for selecting a packet from said assembly buffer means to be sent to said switching network.

A packet format for use in a cluster connected multiprocessing system comprising:

• a command field comprising:
• a first defined pattern of bits which when decoded by a cluster controller within said multiprocessing system will cause a write to a global memory within said cluster controller;
• a second defined pattern of bits which identifies a packet including said command field as carrying a message body;
• a third defined pattern of bits which identifies a packet including said command field as carrying a message header;
• a sequence number field for carrying any of a sequence number of a packet where said command field defines said packet as a message body, and a count of message packets to follow where said command field defines said packet as a message header;
• a destination field for carrying an first address of a destination processing element in said cluster connected multiprocessing system;
• a source field for carrying a second address of a source processing element in said cluster connected system;
• a data field;
• and
• an error correction code field for carrying an error detection and correction code.