Microsemi Semiconductor ULC
Ottawa, CA· latest recorded location
Microsemi Semiconductor ULC is named on 46 US grants and 32 published applications in this corpus. Its most frequent classification is H03L (Automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or).
- Granted patents
- 46
- Published applications
- 32
- Inventors
- 40
- Granted in 2026 so far
- 0
- Most recent grant
- 27 May 2025
Filings by year
| Year | Granted patents | Published applications |
|---|---|---|
| 2012 | 1 | 0 |
| 2013 | 4 | 2 |
| 2014 | 3 | 3 |
| 2015 | 9 | 6 |
| 2016 | 4 | 11 |
| 2017 | 5 | 2 |
| 2018 | 9 | 5 |
| 2019 | 4 | 1 |
| 2020 | 2 | 0 |
| 2021 | 3 | 1 |
| 2022 | 1 | 1 |
| 2023 | 0 | 0 |
| 2024 | 0 | 0 |
| 2025 | 1 | 0 |
By publication year.
Technology areas
Share of 78 documents
- H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or51
- H04LDigital communication20
- H04JMultiplex communication19
- G06FComputing and data processing17
- H03KPulse technique11
- H03HImpedance networks5
- H03MCoding5
- H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements4
- G01RMeasuring electric variables3
- G04FTime-interval measuring2
Recent patents
- Phase and frequency error processing27 May 2025US 12,316,728 B2
- Systems and methods for transporting constant bit rate client signals over a packet transport network1 Feb 2022US 11,239,933 B2
- Circuit and method for generating temperature-stable clocks using ordinary oscillators27 Apr 2021US 10,992,301 B1
- Techniques for routing electrical signals through electrical components and related methods20 Apr 2021US 10,986,730 B2
- Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits9 Feb 2021US 10,917,097 B1
- Phase and frequency error processing20 Oct 2022US 2022/0337387 A1
- Systems and methods for transporting constant bit rate client signals over a packet transport network29 Jul 2021US 2021/0234625 A1
- Digital Phase Locked Loop Clock Synthesizer with Image Cancellation25 Apr 2019US 2019/0123723 A1
- Clock Synthesizer with Hitless Reference Switching and Frequency Stabilization15 Nov 2018US 2018/0329450 A1
- Clock synthesizer with integral non-linear interpolation (inl) distortion compensation19 Jul 2018US 2018/0205370 A1
Most cited
By later US patents
- Embedded time of day receiver for clock transmission38US 10,715,307 B12020
- Circuits and methods for transferring two differentially encoded client clock domains over a third carrier clock domain between integrated circuits32US 10,917,097 B12021
- Phase locked loop with precise phase and frequency slope limiter24US 8,957,711 B22015
- Timing recovery over packet networks20US 8,483,244 B22013
- PLL system with master and slave devices19US 10,007,639 B22018