Clock Synthesizer with Hitless Reference Switching and Frequency Stabilization
AssigneeMicrosemi Semiconductor ULC
InventorsQu Gary JIN, Chao ZHAO
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Abstract
A clock synthesizer for synthesizing an output clock locked to a selected reference clock input has a pair of phase locked loops locked to respective reference clock inputs first generating first and second frequencies. One of the frequencies is selected to control a controlled oscillator for generating an output clock. The frequency offset between the first and second frequencies at the time of switching is stored and added to the frequency controlling the controlled oscillator.
Claims20
A clock synthesizer for synthesizing an output clock locked to a selected reference clock input, comprising:
- a first phase locked loop for generating a first frequency locked to a first selected reference clock input;
- a second phase locked loop for generating a second frequency locked to a second selected reference clock input;
- a controlled oscillator for generating the output clock;
- a first switch responsive to a switch signal for selecting said first or second frequency to control said controlled oscillator;
- a frequency tracker for storing a frequency offset between said first and second frequencies at the time of switching said reference clock inputs;
- and
- a first adder for adding said frequency offset to said first or second frequency controlling said controlled oscillator.
The clock synthesizer of 5, wherein said attenuator comprises a delay register for storing a value that gradually increments until it reaches said stored frequency offset, and a second subtractor for offsetting said incrementing value against said stored frequency offset.
The clock synthesizer of 6, wherein said attenuator further comprises:
- a magnitude/sign block for extracting the magnitude and sign of said stored frequency offset;
- a multiplier for multiplying the value stored in said delay register by the extracted sign;
- a difference block for extracting the difference between said magnitude and the value stored in said delay register;
- and
- a switch for applying an increment df to the currently stored value in said delay register while the difference between said magnitude and the value stored in said delay register is greater than zero.
The clock synthesizer of 7, wherein said switch for applying an increment df to the currently stored value in said delay register is applied to the first input of a third adder whose second input receives the current value stored in said register, and whose output is applied to the input of said register.
A method of synthesizing an output clock from a selected reference clock input, comprising:
- generating a first frequency in a first phase locked loop locked to a first selected reference clock input;
- generating a second frequency in a second phase locked loop locked to a second selected reference clock input;
- selecting one of said first or second frequencies to control a controlled oscillator arranged to synthesize the output clock;
- switching to the other of said first or second frequencies to control said controlled oscillator;
- storing a frequency offset between said first and second frequencies at the time of switching said reference clock inputs;
- and
- adding said stored frequency offset to said first or second frequency controlling said controlled oscillator.
Dependencies are inferred from the claim text.